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Sequential element design with built-in soft error resilience

Published: 01 December 2006 Publication History
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  • Abstract

    This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements.

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    Published In

    cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 14, Issue 12
    December 2006
    108 pages

    Publisher

    IEEE Educational Activities Department

    United States

    Publication History

    Published: 01 December 2006
    Received: 30 August 2005

    Author Tags

    1. Circuit simulation
    2. circuit simulation
    3. error correction
    4. fault injection
    5. sequential element design
    6. soft error rate (SER)

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    • (2022)High Reliability Soft Error Hardened Latch Designfor Nanoscale CMOS Technology using PVT VariationWireless Personal Communications: An International Journal10.1007/s11277-022-10033-4128:2(1471-1487)Online publication date: 31-Oct-2022
    • (2020)Exploring a bayesian optimization framework compatible with digital standard flow for soft-error-tolerant circuitProceedings of the 57th ACM/EDAC/IEEE Design Automation Conference10.5555/3437539.3437676(1-6)Online publication date: 20-Jul-2020
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