research-article

Variability driven gate sizing for binning yield optimization

Authors:

Azadeh Davoodi,

Ankur SrivastavaAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16, Issue 6

Pages 683 - 692

https://doi.org/10.1109/TVLSI.2008.2000252

Published: 01 June 2008 Publication History

Abstract

High performance applications are highly affected by process variations due to considerable spread in their expected frequencies after fabrication. Typically "binning" is applied to those chips that are not meeting their performance requirement after fabrication. Using binning, such failing chips are sold at a loss (e.g., proportional to the degree that they are failing their performance requirement). This paper discusses a gate-sizing algorithm to minimize "yield-loss" associated with binning. We propose a binning yield-loss function as a suitable objective to be minimized. We show this objective is convex with respect to the size variables and consequently can be optimally and efficiently solved. These contributions are yet made without making any specific assumptions about the sources of variability or how they are modeled. We show computation of the binning yield-loss can be done via any desired statistical static timing analysis (SSTA) tool. The proposed technique is compared with a recently proposed sensitivity-based statistical sizer, a deterministic sizer with worst-case variability estimate, and a deterministic sizer with relaxed area constraint. We show consistent improvement compared to the sensitivity-based approach in quality of solution (final binning yield-loss value) as well as huge run-time gain. Moreover, we show that a deterministic sizer with a relaxed area constraint will also result in reasonably good binning yield-loss values for the extra area overhead.

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Cited By

Han QXu QJone W(2018)SERAIntegration, the VLSI Journal10.1016/j.vlsi.2017.08.00760:C(1-12)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2017.08.007
S RVasudevan V(2016)Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield GradientACM Transactions on Design Automation of Electronic Systems10.1145/289681921:4(1-27)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2896819
Guo JDohler MKim WTsoi AZheng K(2016)Mobile big data [Guest editorial]IEEE Network: The Magazine of Global Internetworking10.1109/MNET.2016.747433730:3(4-5)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/MNET.2016.7474337
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Variability driven gate sizing for binning yield optimization

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 16, Issue 6

June 2008

174 pages

ISSN:1063-8210

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Copyright © 2008.

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IEEE Educational Activities Department

United States

Publication History

Published: 01 June 2008

Revised: 06 March 2007

Received: 01 May 2006

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Cited By

Han QXu QJone W(2018)SERAIntegration, the VLSI Journal10.1016/j.vlsi.2017.08.00760:C(1-12)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2017.08.007
S RVasudevan V(2016)Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield GradientACM Transactions on Design Automation of Electronic Systems10.1145/289681921:4(1-27)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2896819
Guo JDohler MKim WTsoi AZheng K(2016)Mobile big data [Guest editorial]IEEE Network: The Magazine of Global Internetworking10.1109/MNET.2016.747433730:3(4-5)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/MNET.2016.7474337
Casagrande TRanganathan NNebel WAtienza D(2015)GTFUZZProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755908(677-682)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755908
Mengying Zhao Orailoglu AXue C(2015)Joint Profit and Process Variation Aware High Level Synthesis With Speed BinningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.234949323:9(1640-1650)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2349493
Mengying ZAlex OJason XMacii E(2013)Profit maximization through process variation aware high level synthesis with speed binningProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485335(176-181)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485335
Rebaud BBelleville MBeigné EBernard CRobert MMaurine PAzemard N(2011)Timing slack monitoring under process and environmental variationsMicroelectronics Journal10.1016/j.mejo.2011.02.00542:5(718-732)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1016/j.mejo.2011.02.005
Gong MZhou HTao JZeng XRoychowdhury J(2009)Binning optimization based on SSTA for transparently-latched circuitsProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687462(328-335)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687462

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