research-article

A General Digit-Serial Architecture for Montgomery Modular Multiplication

Authors:

Serdar Suer Erdem,

Anil CelebiAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 25, Issue 5

Pages 1658 - 1668

https://doi.org/10.1109/TVLSI.2017.2652979

Published: 01 May 2017 Publication History

Abstract

The Montgomery algorithm is a fast modular multiplication method frequently used in cryptographic applications. This paper investigates the digit-serial implementations of the Montgomery algorithm for large integers. A detailed analysis is given and a tight upper bound is presented for the intermediate results obtained during the digit-serial computation. Based on this analysis, an efficient digit-serial Montgomery modular multiplier architecture using carry save adders is proposed and its complexity is presented. In this architecture, pipelined carry select adders are used to perform two final tasks: adding carry save vectors representing the modular product and subtracting the modulus from this addition, if further reduction is needed. The proposed architecture can be designed for any digit size \(\delta \) and modulus \(\theta \) . This paper also presents logic formulas for the bits of the precomputation \(-\theta ^{-1}\bmod 2^{\delta }\) used in the Montgomery algorithm for \(\delta \leq 8\) . Finally, evaluation of the proposed architecture on Virtex 7 FPGAs is presented.

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Cited By

Zhang BCheng ZPedram M(2024)Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.336800232:5(897-910)Online publication date: 29-Feb-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3368002
Zhang BCheng ZPedram M(2022)High-Radix Design of a Scalable Montgomery Modular Multiplier With Low LatencyIEEE Transactions on Computers10.1109/TC.2021.305299971:2(436-449)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1109/TC.2021.3052999
Zhang BCheng ZPedram M(2021)A high-performance low-power barrett modular multiplier for cryptosystemsProceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design10.1109/ISLPED52811.2021.9502490(1-6)Online publication date: 26-Jul-2021
https://dl.acm.org/doi/10.1109/ISLPED52811.2021.9502490

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 25, Issue 5

May 2017

200 pages

ISSN:1063-8210

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Copyright © 2017.

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IEEE Educational Activities Department

United States

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Published: 01 May 2017

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Cited By

Zhang BCheng ZPedram M(2024)Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.336800232:5(897-910)Online publication date: 29-Feb-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3368002
Zhang BCheng ZPedram M(2022)High-Radix Design of a Scalable Montgomery Modular Multiplier With Low LatencyIEEE Transactions on Computers10.1109/TC.2021.305299971:2(436-449)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1109/TC.2021.3052999
Zhang BCheng ZPedram M(2021)A high-performance low-power barrett modular multiplier for cryptosystemsProceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design10.1109/ISLPED52811.2021.9502490(1-6)Online publication date: 26-Jul-2021
https://dl.acm.org/doi/10.1109/ISLPED52811.2021.9502490

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