research-article

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond

Authors:

Trong Huynh-Bao,

Julien Ryckaert,

Abdelkarim Mercha,

Diederik Verkest,

Aaron Voon-Yew Thean,

Piet WambacqAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 25, Issue 5

Pages 1669 - 1680

https://doi.org/10.1109/TVLSI.2017.2647853

Published: 01 May 2017 Publication History

Abstract

In an increasing interconnect resistance era and aggressive metal pitch scaling, the elevating RC delay could significantly shadow the improvements from advanced device architectures and become a severe design issue. This paper will holistically analyze the interplay between transistors and interconnect delay and the variability induced by back-end-of-line (BEOL) process for the 5-nm node. A global sensitivity analysis using Monte Carlo simulation is employed as a powerful tool for understanding the significance of different variation sources and propagating these process uncertainties to circuit performance and parametric yield. For the BEOL integration process, our results show that dielectric \({\kappa }\) -value is the most sensitive parameter. Regarding the patterning options, the BEOL process using self-aligned quadruple pattering with positive tone process requires more than a \(4\times \) process margin and suffers from 50% parametric yield loss. The required guardband for litho-etch litho-etch becomes as critical as for the self-aligned double patterning process when the overlay control is \(6\times \) higher than the critical dimension control. For trench patterning using spacer-defined techniques, a negative tone process is required to achieve a large process window. From a design perspective, the wire length in SoC can be optimized using a disruptive architecture as a vertical FET, which could potentially reduce the average wire length by 11%.

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Cited By

Xu JHan ZJin LWu SYan HShi LAmrouch HHu JGarg SLin Y(2024)FACT: Fast and Accurate Multi-Corner Predictor for Timing Closure in Commercial EDA FlowsProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685941(1-7)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685941
Ahn JChang KChoi KKim TPark H(2024)DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality EnhancementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337011043:8(2493-2506)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3370110
Jeong EKim TPark H(2023)Eliminating Minimum Implant Area Violations With Design Quality PreservationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.322555131:5(611-621)Online publication date: 1-May-2023
https://dl.acm.org/doi/10.1109/TVLSI.2022.3225551

Index Terms

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond
1. Hardware
  1. Hardware validation

Index terms have been assigned to the content through auto-classification.

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 25, Issue 5

May 2017

200 pages

ISSN:1063-8210

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Copyright © 2017.

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IEEE Educational Activities Department

United States

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Published: 01 May 2017

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Cited By

Xu JHan ZJin LWu SYan HShi LAmrouch HHu JGarg SLin Y(2024)FACT: Fast and Accurate Multi-Corner Predictor for Timing Closure in Commercial EDA FlowsProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685941(1-7)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685941
Ahn JChang KChoi KKim TPark H(2024)DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality EnhancementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337011043:8(2493-2506)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3370110
Jeong EKim TPark H(2023)Eliminating Minimum Implant Area Violations With Design Quality PreservationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.322555131:5(611-621)Online publication date: 1-May-2023
https://dl.acm.org/doi/10.1109/TVLSI.2022.3225551
Jeong EPark HKim TBolchini CO'Connor IVerbauwhede IWille R(2022)A systematic removal of minimum implant area violations under timing constraintProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540063(933-938)Online publication date: 14-Mar-2022
https://dl.acm.org/doi/10.5555/3539845.3540063

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