research-article

Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization

Authors:

Seid Hadi Rasouli,

Kaustav BanerjeeAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 505 - 512

https://doi.org/10.1145/1687399.1687495

Published: 02 November 2009 Publication History

Abstract

FinFET is considered as the most likely candidate to substitute bulk CMOS technology. FinFET-based design, however, requires special attention due to its exclusive properties such as width quantization and electrical confinement (quantum-mechanical effect) even in subthreshold regime. Considering these exclusive properties of FinFETs, the sources of process variations and their effects on FinFET-based circuit characteristics can be significantly different from that in bulk CMOS devices. This paper identifies a new source of random process variation due to the gate work-function variation and resulting electrical confinement in emerging high-k/metal-gate FinFET devices. In order to capture the effect of the variations on the characteristics of multifin FinFETs (considering their width quantization property), this paper also presents a new statistical framework to accurately predict the effective threshold voltage of multifin FinFET devices. This framework is subsequently used to predict the leakage profile of FinFET-based SRAM cells. Since FinFETs are optimal for ultra-low-voltage operations due to near-ideal subthreshold swing (60 mV/dec), we focus on FinFET-based SRAM (including subthreshold SRAM) design. Contrary to the low sensitivity of the static noise margin (SNM) to the width of the pull-down devices in bulk-CMOS subthreshold SRAMs, our analysis shows, for the first time, the significant impact of employing multifin pull-down devices on the SNM of subthreshold FinFET SRAMs.

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Cited By

Zimpeck AMeinhardt CArtola LReis RZimpeck AMeinhardt CArtola LReis R(2021)Reliability Challenges in FinFETsMitigating Process Variability and Soft Errors at Circuit-Level for FinFETs10.1007/978-3-030-68368-9_3(29-63)Online publication date: 4-Jan-2021
https://doi.org/10.1007/978-3-030-68368-9_3
Perez-Rivera ZTlelo-Cuautle EChampac V(2020)Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process VariationsTechnologies10.3390/technologies80200258:2(25)Online publication date: 13-May-2020
https://doi.org/10.3390/technologies8020025
Jeong HOh SOh TKim HPark CRim WSong TJung S(2019)Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy SavingIEEE Journal of Solid-State Circuits10.1109/JSSC.2018.288372554:3(896-906)Online publication date: Mar-2019
https://doi.org/10.1109/JSSC.2018.2883725
Show More Cited By

Index Terms

Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

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cover image ACM Conferences

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
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IEEE Council on Electronic Design Automation (CEDA)

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New York, NY, United States

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Published: 02 November 2009

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ICCAD '09

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ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Zimpeck AMeinhardt CArtola LReis RZimpeck AMeinhardt CArtola LReis R(2021)Reliability Challenges in FinFETsMitigating Process Variability and Soft Errors at Circuit-Level for FinFETs10.1007/978-3-030-68368-9_3(29-63)Online publication date: 4-Jan-2021
https://doi.org/10.1007/978-3-030-68368-9_3
Perez-Rivera ZTlelo-Cuautle EChampac V(2020)Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process VariationsTechnologies10.3390/technologies80200258:2(25)Online publication date: 13-May-2020
https://doi.org/10.3390/technologies8020025
Jeong HOh SOh TKim HPark CRim WSong TJung S(2019)Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy SavingIEEE Journal of Solid-State Circuits10.1109/JSSC.2018.288372554:3(896-906)Online publication date: Mar-2019
https://doi.org/10.1109/JSSC.2018.2883725
Prasanth KRamireddy MKeerthi priya TRavindrakumar S(2019)High Speed, Low Matchline Voltage Swing and Search Line Activity TCAM Cell Array Design in 14 nm FinFET TechnologyEmerging Trends in Electrical, Communications, and Information Technologies10.1007/978-981-13-8942-9_38(465-473)Online publication date: 25-Sep-2019
https://doi.org/10.1007/978-981-13-8942-9_38
Senthil Kumar VRavindrakumar S(2019)Design of an Area-Efficient FinFET-Based Approximate Multiplier in 32-nm Technology for Low-Power ApplicationSoft Computing and Signal Processing10.1007/978-981-13-3393-4_52(505-513)Online publication date: 14-Feb-2019
https://doi.org/10.1007/978-981-13-3393-4_52
Kaushik BDasgupta SPal P(2017) Design Metric Improvement of a Dual- k –Based SRAM Cell Spacer Engineered FinFET Architectures10.1201/9781315191089-6(91-119)Online publication date: 16-Jun-2017
https://doi.org/10.1201/9781315191089-6
Kaushik BDasgupta SPal P(2017)Tri-Gate FinFET Technology and Its AdvancementSpacer Engineered FinFET Architectures10.1201/9781315191089-3(11-36)Online publication date: 16-Jun-2017
https://doi.org/10.1201/9781315191089-3
Wu PLin MLi XHo T(2016)Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio MatchingACM Transactions on Design Automation of Electronic Systems10.1145/285603121:3(1-22)Online publication date: 19-Apr-2016
https://dl.acm.org/doi/10.1145/2856031
Khatamifard SResch MKim NKarpuzcu U(2016)VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753353(654-661)Online publication date: Oct-2016
https://doi.org/10.1109/ICCD.2016.7753353
Wu PLin MLi XHo TDavoodi AYoung E(2015)Common-Centroid FinFET Placement Considering the Impact of Gate MisalignmentProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717769(25-31)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2717769
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