article

Low-Latency Virtual-Channel Routers for On-Chip Networks

Authors:

Robert Mullins,

Simon MooreAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 32, Issue 2

Page 188

https://doi.org/10.1145/1028176.1006717

Published: 02 March 2004 Publication History

Abstract

The on-chip communication requirements of manysystems are best served through the deployment of a regularchip-wide network. This paper presents the design of alow-latency on-chip network router for such applications.We remove control overheads (routing and arbitrationlogic) from the critical path in order to minimise cycle-timeand latency. Simulations illustrate that dramatic cycle timeimprovements are possible without compromising routerefficiency. Furthermore, these reductions permit flits to berouted in a single cycle, maximising the effectiveness of therouter's limited buffering resources.

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 32, Issue 2

ISCA 2004

March 2004

373 pages

ISSN:0163-5964

DOI:10.1145/1028176

Issue’s Table of Contents

ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture
June 2004
373 pages
ISBN:0769521436

Copyright © 2004 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 March 2004

Published in SIGARCH Volume 32, Issue 2

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Mulajkar ASinha SPatel G(2023)Deflection routing mechanism using BLESS and BBUS NoCMaterials Today: Proceedings10.1016/j.matpr.2021.06.23480(2289-2292)Online publication date: 2023
https://doi.org/10.1016/j.matpr.2021.06.234
Effiong CSassatelli GGamatié A(2022)Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance InterconnectMicromachines10.3390/mi1312224613:12(2246)Online publication date: 17-Dec-2022
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Jiao JHe YCao TKondo M(2022)Enabling circuit-switching in modern on-chip networksMicroprocessors and Microsystems10.1016/j.micpro.2022.10471295(104712)Online publication date: Nov-2022
https://doi.org/10.1016/j.micpro.2022.104712
Bamberg LJoseph JGarcía-Ortiz APionteck TBamberg LJoseph JGarcía-Ortiz APionteck T(2022)Interconnect Architectures for 3D Technologies3D Interconnect Architectures for Heterogeneous Technologies10.1007/978-3-030-98229-4_2(27-47)Online publication date: 12-Mar-2022
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Ben Abdallah AN. Dang KBen Abdallah ADang K(2022)Communication Networks for Neuromorphic SystemsNeuromorphic Computing Principles and Organization10.1007/978-3-030-92525-3_5(79-126)Online publication date: 7-Apr-2022
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Ma WGao XGao YYu N(2021)A Latency-Optimized Network-on-Chip with Rapid Bypass ChannelsMicromachines10.3390/mi1206062112:6(621)Online publication date: 27-May-2021
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He YJiao JKondo M(2021)Local Traffic-Based Energy-Efficient Hybrid Switching for On-Chip Networks2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP52278.2021.00039(198-206)Online publication date: Mar-2021
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Jayshree Seetharaman GPati D(2021)Reliable Fault-Tolerance Routing Technique for Network-on-Chip InterconnectIntelligent Sustainable Systems10.1007/978-981-16-2422-3_60(767-775)Online publication date: 27-Aug-2021
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