article

Fingerprinting: bounding soft-error detection latency and bandwidth

Authors:

Jared C. Smolens,

Andreas G. NowatzykAuthors Info & Claims

ACM SIGPLAN Notices, Volume 39, Issue 11

Pages 224 - 234

https://doi.org/10.1145/1037187.1024420

Published: 07 October 2004 Publication History

Abstract

Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection technique, called fingerprinting, that detects differences in execution across a dual modular redundant (DMR) processor pair. Fingerprinting summarizes a processor's execution history in a hash-based signature; differences between two mirrored processors are exposed by comparing their fingerprints. Fingerprinting tightly bounds detection latency and greatly reduces the interprocessor communication bandwidth required for checking. This paper presents a study that evaluates fingerprinting against a range of current approaches to error detection. The result of this study shows that fingerprinting is the only error detection mechanism that simultaneously allows high-error coverage, low error detection bandwidth, and high I/O performance.

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Latifi SZamirai BMahlke S(2022)SoftFusion: A Low-Cost Approach to Enhance Reliability of Object Detection Applications2022 IEEE 40th International Conference on Computer Design (ICCD)10.1109/ICCD56317.2022.00057(344-351)Online publication date: Oct-2022
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Chatterjee NPaul SChattopadhyay S(2018)Task mapping and scheduling for network-on-chip based multi-core platform with transient faultsJournal of Systems Architecture10.1016/j.sysarc.2018.01.00283(34-56)Online publication date: Feb-2018
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Fingerprinting: bounding soft-error detection latency and bandwidth

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Fingerprinting: bounding soft-error detection latency and bandwidth
ASPLOS XI: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems

Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection technique, called fingerprinting, that detects differences in execution across a ...
Fingerprinting: bounding soft-error detection latency and bandwidth
ASPLOS 2004

Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection technique, called fingerprinting, that detects differences in execution across a ...
Fingerprinting: bounding soft-error detection latency and bandwidth
ASPLOS '04

Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection technique, called fingerprinting, that detects differences in execution across a ...

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Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 39, Issue 11

ASPLOS '04

November 2004

283 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/1037187

Issue’s Table of Contents

ASPLOS XI: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
October 2004
296 pages
ISBN:1581138040
DOI:10.1145/1024393
General Chair:
Shubu Mukherjee
Intel Corporation
,
Program Chair:
Kathryn S. McKinley
University of Texas at Austin

Copyright © 2004 ACM.

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Association for Computing Machinery

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Published: 07 October 2004

Published in SIGPLAN Volume 39, Issue 11

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Cited By

Latifi SZamirai BMahlke S(2022)SoftFusion: A Low-Cost Approach to Enhance Reliability of Object Detection Applications2022 IEEE 40th International Conference on Computer Design (ICCD)10.1109/ICCD56317.2022.00057(344-351)Online publication date: Oct-2022
https://doi.org/10.1109/ICCD56317.2022.00057
Ozturk ZTopcuoglu HKandemir M(2022)Studying error propagation on application data structure and hardwareThe Journal of Supercomputing10.1007/s11227-022-04625-x78:17(18691-18724)Online publication date: 13-Jun-2022
https://doi.org/10.1007/s11227-022-04625-x
Chatterjee NPaul SChattopadhyay S(2018)Task mapping and scheduling for network-on-chip based multi-core platform with transient faultsJournal of Systems Architecture10.1016/j.sysarc.2018.01.00283(34-56)Online publication date: Feb-2018
https://doi.org/10.1016/j.sysarc.2018.01.002
Gupta MLowell DKalamatianos JRaasch SSridharan VTullsen DGupta R(2017)Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant MultithreadingProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062212(1-6)Online publication date: 18-Jun-2017
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Zhou JYin MLi ZCao KYan JWei TChen MFu X(2017)Fault-Tolerant Task Scheduling for Mixed-Criticality Real-Time SystemsJournal of Circuits, Systems and Computers10.1142/S021812661750016526:01(1750016)Online publication date: Jan-2017
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Venkatesha SParthasarathi R(2024)Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and ReliabilityACM Computing Surveys10.1145/366367256:11(1-76)Online publication date: 6-May-2024
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