Article

A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications

Authors:

A. Papanikolaou,

F. CatthoorAuthors Info & Claims

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 117 - 122

https://doi.org/10.1145/1084834.1084866

Published: 19 September 2005 Publication History

Abstract

Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yield. In this paper we propose a broadly applicable system-level technique that can guarantee parametric yield on the memory organization and which minimizes the energy overhead associated to variability in the conventional design process. It is based on offering configuration capabilities at the memory-level and exploiting them at the system-level. This technique can decrease by up to a factor of 5 the energy overhead that is introduced by state-of-the-art process variability compensation techniques, including statistical timing analysis. In this way we obtain results close to the ideal nominal design again.

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Cited By

Kadayif ITurkcan MKiziltepe SOzturk O(2013)Hardware/software approaches for reducing the process variation impact on instruction fetchesACM Transactions on Design Automation of Electronic Systems10.1145/248977818:4(1-23)Online publication date: 25-Oct-2013
https://dl.acm.org/doi/10.1145/2489778
Pasricha SPark YDutt NKurdahi F(2009)System-level PVT variation-aware power exploration of on-chip communication architecturesACM Transactions on Design Automation of Electronic Systems10.1145/1497561.149756314:2(1-25)Online publication date: 7-Apr-2009
https://dl.acm.org/doi/10.1145/1497561.1497563
Mutyam MWang FKrishnan RNarayanan VKandemir MXie YIrwin M(2009)Process-Variation-Aware Adaptive Cache Architecture and ManagementIEEE Transactions on Computers10.1109/TC.2009.3058:7(865-877)Online publication date: 1-Jul-2009
https://dl.acm.org/doi/10.1109/TC.2009.30
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Index Terms

A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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cover image ACM Conferences

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

September 2005

356 pages

ISBN:1595931619

DOI:10.1145/1084834

General Chairs:
Petru Eles
Linköping University, Sweden
,
Axel Jantsch
Royal Institute of Technology, Sweden
,
Program Chair:
Reinaldo Bergamaschi
IBM T. J. Watson Research Center

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 19 September 2005

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CODES/ISSS05

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CODES/ISSS05: Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

September 19 - 21, 2005

NJ, Jersey City, USA

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CODES+ISSS '05 Paper Acceptance Rate 50 of 200 submissions, 25%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Kadayif ITurkcan MKiziltepe SOzturk O(2013)Hardware/software approaches for reducing the process variation impact on instruction fetchesACM Transactions on Design Automation of Electronic Systems10.1145/248977818:4(1-23)Online publication date: 25-Oct-2013
https://dl.acm.org/doi/10.1145/2489778
Pasricha SPark YDutt NKurdahi F(2009)System-level PVT variation-aware power exploration of on-chip communication architecturesACM Transactions on Design Automation of Electronic Systems10.1145/1497561.149756314:2(1-25)Online publication date: 7-Apr-2009
https://dl.acm.org/doi/10.1145/1497561.1497563
Mutyam MWang FKrishnan RNarayanan VKandemir MXie YIrwin M(2009)Process-Variation-Aware Adaptive Cache Architecture and ManagementIEEE Transactions on Computers10.1109/TC.2009.3058:7(865-877)Online publication date: 1-Jul-2009
https://dl.acm.org/doi/10.1109/TC.2009.30
Sanz CPrieto MGómez JPapanikolaou AMiranda MCatthoor F(2008)Combining system scenarios and configurable memories to tolerate unpredictabilityACM Transactions on Design Automation of Electronic Systems10.1145/1367045.136705813:3(1-7)Online publication date: 25-Jul-2008
https://dl.acm.org/doi/10.1145/1367045.1367058
Pasricha SPark YKurdahi FDutt N(2008)Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication ArchitecturesProceedings of the 21st International Conference on VLSI Design10.1109/VLSI.2008.14(363-370)Online publication date: 4-Jan-2008
https://dl.acm.org/doi/10.1109/VLSI.2008.14
Jang HKashif APark MChung S(2008)Reliable Cache Memory Design for Sensor NetworksProceedings of the 2008 Third International Conference on Convergence and Hybrid Information Technology - Volume 0110.1109/ICCIT.2008.125(651-656)Online publication date: 11-Nov-2008
https://dl.acm.org/doi/10.1109/ICCIT.2008.125
Wang HCatthoor FMiranda MDehaene W(2008)Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-OffsJournal of Signal Processing Systems10.1007/s11265-007-0147-552:2(193-210)Online publication date: 1-Aug-2008
https://dl.acm.org/doi/10.1007/s11265-007-0147-5
Papanikolaou AWang HMiranda MCatthoor FDehaene W(2008)Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System DesignVLSI-SoC: Research Trends in VLSI and Systems on Chip10.1007/978-0-387-74909-9_8(119-141)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74909-9_8
Mutyam MNarayanan VLauwereins RMadsen J(2007)Working with process variation aware cachesProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266615(1152-1157)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266615
Wang HMiranda MCatthoor FDehaene W(2007)Impact of Random Soft Oxide Breakdown on SRAM Energy/Delay DriftIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2007.9104447:4(581-591)Online publication date: Dec-2007
https://doi.org/10.1109/TDMR.2007.910444
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