research-article

Making Typical Silicon Matter with Razor

Authors:

Todd Austin,

David Blaauw,

Trevor Mudge,

Krisztián FlautnerAuthors Info & Claims

Computer, Volume 37, Issue 3

Pages 57 - 65

https://doi.org/10.1109/MC.2004.1274005

Published: 01 March 2004 Publication History

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Abstract

Voltage scaling has emerged as a powerful technology for addressing the power challenges that current on-chip densities pose. Razor is a voltage-scaling technology based on dynamic, in-situ detection and correction of circuit-timing errors. Razor permits design optimizations that tune theenergy in a microprocessor pipeline to typical circuit-operational levels. This eliminates the voltage margins that traditional worst-case design methodologies require and lets digital systems run correctly and robustly at the edge of minimum power consumption.Occasional heavyweight computations may fail and require additional time and energy for recovery, but the optimized pipeline requires significantly less energy overall than traditional designs.

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Kondguli SHuang M(2018)A Case for a More Effective, Power-Efficient Turbo BoostingACM Transactions on Architecture and Code Optimization10.1145/317043315:1(1-22)Online publication date: 22-Mar-2018
https://dl.acm.org/doi/10.1145/3170433
Giesen HGojman BRubin RKim JDehon A(2018)Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)ACM Transactions on Reconfigurable Technology and Systems10.1145/315822911:1(1-23)Online publication date: 26-Jan-2018
https://dl.acm.org/doi/10.1145/3158229
Semião JCabral RSantos MTeixeira ITeixeira J(2018)Performance Sensor for Reliable OperationUniversal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments 10.1007/978-3-319-92052-8_28(347-365)Online publication date: 15-Jul-2018
https://dl.acm.org/doi/10.1007/978-3-319-92052-8_28
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Index Terms

Making Typical Silicon Matter with Razor
1. Hardware

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Published In

Computer Volume 37, Issue 3

March 2004

94 pages

ISSN:0018-9162

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 March 2004

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Kondguli SHuang M(2018)A Case for a More Effective, Power-Efficient Turbo BoostingACM Transactions on Architecture and Code Optimization10.1145/317043315:1(1-22)Online publication date: 22-Mar-2018
https://dl.acm.org/doi/10.1145/3170433
Giesen HGojman BRubin RKim JDehon A(2018)Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)ACM Transactions on Reconfigurable Technology and Systems10.1145/315822911:1(1-23)Online publication date: 26-Jan-2018
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Semião JCabral RSantos MTeixeira ITeixeira J(2018)Performance Sensor for Reliable OperationUniversal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments 10.1007/978-3-319-92052-8_28(347-365)Online publication date: 15-Jul-2018
https://dl.acm.org/doi/10.1007/978-3-319-92052-8_28
Stanley-Marbell PRinard M(2017)Error-Efficient Computing SystemsFoundations and Trends in Electronic Design Automation10.1561/100000004911:4(362-461)Online publication date: 18-Dec-2017
https://dl.acm.org/doi/10.1561/1000000049
Valadimas STsiatouhas YArapoyanni A(2016)Timing Error Tolerance in Small Core Designs for SoC ApplicationsIEEE Transactions on Computers10.1109/TC.2015.242056265:2(654-663)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1109/TC.2015.2420562
De VKahng AKarnik TLiu BMaleki MWang L(2015)Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI DesignACM Journal on Emerging Technologies in Computing Systems10.1145/274634112:3(1-19)Online publication date: 21-Sep-2015
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Shi KBoland DConstantinides G(2015)Imprecise Datapath DesignACM Transactions on Reconfigurable Technology and Systems10.1145/26295278:2(1-23)Online publication date: 17-Mar-2015
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Valadimas SArapoyanni ASokratis KMichael HTheodoros ADimosthenis AElias CTheodora VMara N(2014)Timing Error Tolerance in Pipeline Based Core DesignsProceedings of the 18th Panhellenic Conference on Informatics10.1145/2645791.2645797(1-6)Online publication date: 2-Oct-2014
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Shi KBoland DStott EBayliss SConstantinides G(2014)Datapath Synthesis for OverclockingProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593118(1-6)Online publication date: 1-Jun-2014
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Sridharan ASechen CJafari RChou PHuang RXie YKarnik T(2013)Low-voltage low-overhead asynchronous logicProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648734(261-266)Online publication date: 4-Sep-2013
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Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Razor: a variability-tolerant design methodology for low-power and robust computing

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