Low-voltage low-overhead asynchronous logic
Pages 261 - 266
Abstract
A new delay-bounded asynchronous logic technique aimed at maximizing reliability at very low voltages is proposed. Compared to previous asynchronous logic approaches, the area and nominal delay overheads are small. Conventional standard cell libraries and conventional logic synthesis tools are used. The bounding delay elements used by the asynchronous controller feature programmable delays that are initially set based on static timing analysis. However, the delay elements are updated on-the-fly during actual operation of the circuit, resulting in strong resiliency even at low voltages and with extreme variations. Several benchmark circuits were implemented with the new asynchronous design flow using the 45nm TI process. Monte Carlo analysis demonstrates the expected resiliency. Compared to the equivalent synchronous circuits, the asynchronous versions have area overheads averaging 40%, although much smaller for large circuits. Nominal delay overheads average about 10%.
References
[1]
Mohammad-Mahdi Bidmeshki, and Roozbeh Jafari, "Low Power Programmable Architecture for Periodic Activity Monitoring," Proc. of ICCPS, April 2013.
[2]
Reza Lotfian and Roozbeh Jafari, "An Ultra-Low Power Hardware Accelerator Architecture for Wearable Computers Using Dynamic Time Warping," Proc. of DATE, March 2013.
[3]
Karl M. Fant and Scott A. Brandt, NULL Convention LogicTM System, US patent 5,305,463, April 19, 1994.
[4]
A. M. Lines and S. Fairbanks, "GasP: a minimal FIFO control," Proc. of ASYNC, 2001, pp. 46--53.
[5]
S. Schuster et. al., "Asynchronous interlocked pipelined CMOS circuits operating at 3.3--4.5 GHz," Proc. ISSCC, 2000, pp. 292--293.
[6]
R. O. Ozdag and P. A. Beerel, "High-Speed QDI Asynchronous Pipelines," IEEE Proc. of ASYNC, 2002, pp. 13--22.
[7]
I. E. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, no. 6, 1989, pp. 720--738.
[8]
Jens Sparso, Asynchronous circuit design: A Tutorial, Technical University of Denmark, 2006, http://www.imm.dtu.dk/~jsp/.
[9]
G. N. Hoyer, G. Yee, and C. Sechen, "Locally Clocked Pipelines and Dynamic Logic," IEEE Trans. on VLSI, vol. 10, 2001, pp. 58--62.
[10]
S. B. Furber and P. Day, "Four-phase micropipeline latch control circuits," IEEE Trans. VLSI, vol. 4, no. 2, 1996, p. 247.
[11]
Montek Singh and Steven M. Nowick "MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines," IEEE Trans. on VLSI, vol. 15, no. 6, 2007, pp. 684--698.
[12]
T. E. Williams and M. A. Horowitz, "A zero-overhead self-timed 160ns 54b CMOS divider," Proc. ISSCC, 1991, p. 98.
[13]
Ik Joon Chang, Sang Phill Park and Roy, K., "Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation," IEEE Journal of Solid-State Circuits, vol. 45, no. 2, pp. 401, 410, Feb. 2010.
[14]
Crop, J., Fairbanks, S., Pawlowski, R. and Chiang, P., "150mV sub-threshold Asynchronous multiplier for low-power sensor applications," Proc. VLSI-DAT, p. 254, April 2010.
[15]
Xiaofei Chang, Yong Lian, "A Quasi-Delay-Insensitive Dual-Rail low-pass filter working in subthreshold region," Proc. of BioCAS, pp. 214--217, Nov. 2010.
[16]
A. Arthurs, Jia Di, "Analysis of ultra-low voltage digital circuits over process variations," Proc. of SubVT, 2012 IEEE, pp. 1--3, Oct. 2012.
[17]
Tsung-Te Liu, Louis Alarcon and Jan Rabaey. "Towards an Ultra Low-Energy Computation with Asynchronous Circuits," Poster, BWRC Winter 2012 Retreat, Jan. 2012.
[18]
J. Cortadella, A. Kondratyev, L. Lavagno, and C. Sotiriou, "Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications", IEEE Trans. on CAD, vol. 25, no. 10, 2006, pp. 1904--1921.
[19]
N. Andrikos, L. Lavagno, D. Pandini, and C. Sotiriou, "A Fully-Automated Desynchronization Flow for Synchronous Circuits," Proc. of DAC, June 2007, pp. 982--985.
[20]
T. Austin, D. Blaauw, T. Mudge, K. Flautner, "Making typical silicon matter with Razor," Computer, vol. 37, no. 3, pp. 57--65, Mar 2004.
[21]
D. Ernst et. al., "Razor: circuit-level correction of timing errors for low-power operation," IEEE Micro, vol. 24, no. 6, p. 10, Nov. 2004.
[22]
Tormene, P., Giorgino, T., Quaglini, S. and Stefanelli, M., "Matching incomplete time series with dynamic time warping: an algorithm and an application to post-stroke rehabilitation," Artificial Intelligence in Medicine, Vol. 45, January 2009, Pages 11--34.
[23]
Liu, R., Zhou, J., Liu, M., Hou, X., "A wearable acceleration sensor system for gait recognition," ICIEA, 2007, pp. 2654--2659.
Index Terms
- Low-voltage low-overhead asynchronous logic
Recommendations
Vertically integrated SOI circuits for low-power and high-performance applications
Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can ...
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
Carbon Nanotube Field Effect Transistors (CNFETs) show great promise as extensions to silicon CMOS. However, CNFET-based circuits will face great fabrication challenges that will translate into important parameter variations and decreased reliability. ...
Bias circuit design for low-voltage cascode transistors
SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems designThis article presents a design methodology for the most simple cascode transistor's bias circuit, i.e. a diode-connected transistor, valid from weak to strong inversion. By taking advantage of a compact MOS transistor model, we show how the circuit can ...
Comments
Information & Contributors
Information
Published In
September 2013
440 pages
ISBN:9781479912353
- General Chairs:
- Pai Chou,
- Ru Huang,
- Program Chairs:
- Yuan Xie,
- Tanay Karnik
Sponsors
Publisher
IEEE Press
Publication History
Published: 04 September 2013
Check for updates
Author Tags
Qualifiers
- Research-article
Conference
ISLPED'13
Sponsor:
ISLPED'13: International Symposium on Low Power Electronics and Design
September 4 - 6, 2013
Beijing, China
Acceptance Rates
Overall Acceptance Rate 398 of 1,159 submissions, 34%
Upcoming Conference
ISLPED '24
- Sponsor:
- sigda
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 40Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 27 Jul 2024
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in