Semião J, Cabral R, Santos M, Teixeira I and Teixeira J. Performance Sensor for Reliable Operation. Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments . (347-365).
Kondguli S and Huang M.
(2018). A Case for a More Effective, Power-Efficient Turbo Boosting. ACM Transactions on Architecture and Code Optimization. 15:1. (1-22). Online publication date: 2-Apr-2018.
Stanley-Marbell P and Rinard M.
(2017). Error-Efficient Computing Systems. Foundations and Trends in Electronic Design Automation. 11:4. (362-461). Online publication date: 18-Dec-2017.
Valadimas S, Tsiatouhas Y and Arapoyanni A.
(2016). Timing Error Tolerance in Small Core Designs for SoC Applications. IEEE Transactions on Computers. 65:2. (654-663). Online publication date: 1-Feb-2016.
De V, Kahng A, Karnik T, Liu B, Maleki M and Wang L.
(2015). Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. ACM Journal on Emerging Technologies in Computing Systems. 12:3. (1-19). Online publication date: 21-Sep-2015.
Shi K, Boland D and Constantinides G.
(2015). Imprecise Datapath Design. ACM Transactions on Reconfigurable Technology and Systems. 8:2. (1-23). Online publication date: 17-Apr-2015.
Valadimas S and Arapoyanni A. Timing Error Tolerance in Pipeline Based Core Designs. Proceedings of the 18th Panhellenic Conference on Informatics. (1-6).
Valadimas S, Tsiatouhas Y, Arapoyanni A and Xarchakos P.
(2013). Effective Timing Error Tolerance in Flip-Flop Based Core Designs. Journal of Electronic Testing: Theory and Applications. 29:6. (795-804). Online publication date: 1-Dec-2013.
Sridharan A, Sechen C and Jafari R. Low-voltage low-overhead asynchronous logic. Proceedings of the 2013 International Symposium on Low Power Electronics and Design. (261-266).
Axer P, Sebastian M and Ernst R. Reliability analysis for MPSoCs with mixed-critical, hard real-time constraints. Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. (149-158).
Sanz Pineda C, Prieto M, Gómez J, Tenllado C and Catthoor F. Statistical approach in a system level methodology to deal with process variation. Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. (115-124).
Carter N, Naeimi H and Gardner D. Design techniques for cross-layer resilience. Proceedings of the Conference on Design, Automation and Test in Europe. (1023-1028).
DeHon A, Quinn H and Carter N. Vision for cross-layer optimization to address the dual challenges of energy and reliability. Proceedings of the Conference on Design, Automation and Test in Europe. (1017-1022).
Rubin R and DeHon A. Choose-your-own-adventure routing. Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays. (23-32).
Sanz C, Prieto M, Gómez J, Papanikolaou A and Catthoor F. System-level process variability compensation on memory organizations. Proceedings of the 2009 Asia and South Pacific Design Automation Conference. (254-259).
Kodi A, Sarathy A, Louri A and Wang J. Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures. Proceedings of the 2009 Asia and South Pacific Design Automation Conference. (1-6).
Garg A and Huang M. A performance-correctness explicitly-decoupled architecture. Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture. (306-317).
Lisboa C, Kastensmidt F and Carro L. Analyzing the effects of the granularity of recomputation based techniques to cope with radiation induced soft errors. Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies. (329-338).
Blome J, Feng S, Gupta S and Mahlke S. Self-calibrating Online Wearout Detection. Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture. (109-122).
Pan Z and Breuer M.
(2007). Estimating Error Rate in Defective Logic Using Signature Analysis. IEEE Transactions on Computers. 56:5. (650-661). Online publication date: 1-May-2007.
Shyam S, Constantinides K, Phadke S, Bertacco V and Austin T. Ultra low-cost defect protection for microprocessor pipelines. Proceedings of the 12th international conference on Architectural support for programming languages and operating systems. (73-82).
Blome J, Gupta S, Feng S and Mahlke S. Cost-efficient soft error protection for embedded microprocessors. Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems. (421-431).
Papanikolaou A, Grabner T, Miranda M, Roussel P and Catthoor F. Yield prediction for architecture exploration in nanometer technology nodes:. Proceedings of the 4th international conference on Hardware/software codesign and system synthesis. (253-258).
Sanz C, Prieto M, Papanikolaou A, Miranda M and Catthoor F. System-level process variability compensation on memory organizations of dynamic applications. Proceedings of the 7th International Symposium on Quality Electronic Design. (376-382).
Wang H, Miranda M, Papanikolaou A, Catthoor F and Dehaene W.
(2005). Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:10. (1127-1135). Online publication date: 1-Oct-2005.
Papanikolaou A, Lobmaier F, Wang H, Miranda M and Catthoor F. A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications. Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. (117-122).
DeHon A and Likharev K. Hybrid CMOS/nanoelectronic digital circuits. Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design. (375-382).
Austin T, Bertacco V, Blaauw D and Mudge T. Opportunities and challenges for better than worst-case design. Proceedings of the 2005 Asia and South Pacific Design Automation Conference. (2-7).
Worm F, Ienne P, Thiran P and De Micheli G.
(2005). A robust self-calibrating transmission scheme for on-chip networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:1. (126-139). Online publication date: 1-Jan-2005.
Worm F, Ienne P and Thiran P. Soft self-synchronising codes for self-calibrating communication. Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design. (440-447).