Statistical approach in a system level methodology to deal with process variation
Authors: 
Concepción Sanz Pineda, Manuel Prieto, Jose Ignacio Gómez, Christian Tenllado, Francky CatthoorAuthors Info & Claims
Concepción Sanz Pineda, Manuel Prieto, Jose Ignacio Gómez, Christian Tenllado, Francky CatthoorAuthors Info & ClaimsPages 115 - 124
Abstract
The impact of process variation in state of the art technology makes traditional(worst case) designs unnecessarily pessimistic, which translates to a suboptimal designs in terms of both energy consumption and performance. In this context, developing variation aware design methodologies becomes a must. These techniques should provide better performance-energy balances while the percentage of faulty products keeps controlled. Furthermore, it would be advisable to consider adaptations of the system during lifetime, in order to provide robustness against ageing. In this paper we propose a design approach which tackles process variation on the memory system by using multimode memories. At design time we perform a heuristic exploration using probabilistic models of these memories, which generates a set of system configurations that minimize energy consumption for a given set of timing constraints. The percentage of systems that will satisfy these deadlines, even under process variation, is taken as a design parameter. Additionally, if system monitors are available, a setup stage optimizes the initial set of configurations for the actual memory parameters. Our simulations show that this methodology provides significant energy savings while still meeting timing constraints
References
[1]
A. M. AbdelHamid, A. Anchlia, S. Mamagkakis, M. C. Miranda, B. Dierickx, and M. Kuijk. A standardized knobs and monitors rtl2rtl insertion methodology for fine grain soc tuning. Digital Systems Design, Euromicro Symposium on, 0:401--408, 2009.
[2]
A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, page 900, Washington, DC, USA, 2003. IEEE Computer Society.
[3]
ATOMIUM. http://www.imec.be/design/atomium/.
[4]
T. Austin, D. Blaauw, T. Mudge, and K. Flautner. Making typical silicon matter with Razor. IEEE Computer, 37(3):57--65, 2004.
[5]
S. Borkar, T. Karnik, and V. De. Design and reliability challenges in nanometer technologies. In DAC'04: Proceedings of the 41st annual conference on Design automation, page 75, New York, NY, USA, 2004. ACM Press.
[6]
M. Dasygenis, E. Brockmeyer, B. Durinck, F. Catthoor, D. Soudris, and A. Thanailakis. A memory hierarchical layer assigning and prefetching technique to overcome the memory performance/energy bottleneck. In DATE '05: Proceedings of the conference on Design, Automation and Test in Europe, pages 946--947, Washington, DC, USA, 2005. IEEE Computer Society.
[7]
F. Catthoor, K. Danckaert et al. Data access and storage management for embedded programmable processors. Springer, Boston MA, 2002.
[8]
C. Forzan and D. Pandini. Statistical static timing analysis: A survey. Integr. VLSI J., 42(3):409--435, 2009.
[9]
S. Gheorghita, T. Baasten, and H. Corporaal. Application scenarios in streaming-oriented embedded system design. In Proceedings of the Intl. Symposium on System-on-Chip, pages 175--178. IEEE, 2006.
[10]
V. Gherman, S. Evain, M. Cartron, N. Seymour, and Y. Bonhomme. System-level hardware-based protection of memories against soft-errors. In Proceedings of the 12th ACM/IEEE Design and Test in Europe Conference (DATE), pages 1222--1225. IEEE, 2009.
[11]
S. Herbert and D. Marculescu. Variation-aware dynamic voltage/frequency scaling. In HPCA, pages 301--312, 2009.
[12]
H.Wang, F. Catthoor, K. Maex, M. Miranda, and W. Dehaene. Systematic analysis of energy and delay impact of very deep submicron process variability effects in embedded SRAM modules. In DATE'05: Proceedings of the conference on Design, automation and test in Europe, pages 914--919, Washington, DC, USA, 2005. IEEE Computer Society.
[13]
S. Kirolos and Y. Massoud. Adaptive SRAM design for dynamic voltage scaling VLSI systems. pages 1297--1300, Aug. 2007.
[14]
A. Lambrechts, T. Vander Aa, M. Jayapala, G. Talavera, A. Leroy, A. Shickova, F. Barat, B. Mei, F. Catthoor, D. Verkest, G. Deconinck, H. Corporaal, F. Robert, and J. C. Bordoll. Design style case study for embedded multi media compute nodes. In RTSS '04: Proceedings of the 25th IEEE International Real-Time Systems Symposium, pages 104--113, Washington, DC, USA, 2004. IEEE Computer Society.
[15]
B. Mohammad, S. Bijansky, A. Aziz, and J. Abraham. Adaptive SRAM memory for low power and high yield. pages 176--181, Oct. 2008.
[16]
S. Mukhopadhyay, K. Kang, H. Mahmoodi, and K. Roy. Design of reliable and self-repairing sram in nano-scale technologies using leakage and delay monitoring. In ITC '05: Proceedings of the 2005 IEEE International Test Conference, pages 1135--1145. IEEE Computer Society, 2005.
[17]
S. Mukhopadhyay, H. Mahmoodi-Meimand, and K. Roy. Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement. In VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on, pages 64--67, June 2004.
[18]
M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers. Matching properties of mos transistors. volume 24, pages 1433--1440, 1989.
[19]
V. Petrescu, M. Pelgrom, H. Veendrick, P. Pavithran, and J. Wieling. Monitors for a signal integrity measurement system. In ESSCIR '06: Proceedings of the 2006 IEEE European Solid-State Circuits Conference, pages 122--125. IEEE Computer Society, 2006.
[20]
C. Sanz, A. Papanikolaou, M. Prieto, J. Gómez, M. Miranda, and F. Catthoor. Combining system scenarios and configurable memories to tolerate unpredictability. ACM Transactions on Design Automation of Electronic Systems (TODAES), 13(3), 2008.
[21]
C. Sanz, M. Prieto, J. I. Gómez, A. Papanikolaou, and F. Catthoor. "system-level process variability compensation on memory organizations: on the scalability of multi-mode memories". In ASP-DAC, pages 254--259. IEEE, 2009.
[22]
Semiconductor Industries Association Roadmap. International Technology Roadmap for Semiconductors, Technical Reports, 2005.
[23]
M. A. Viredaz, M. A. Viredaz, D. A. Wallach, and D. A. Wallach. Power evaluation of a handheld computer: A case study. Technical report, Compaq Western Research Laboratory, 2001.
[24]
H. Wang, M. Miranda, A. Papanikolaou, and F. Catthoor. Variable tapered pareto buffer design and implementation techniques allowing run-time conguration for low power embedded SRAMs. IEEE Trans. VLSI., 13(10):1127--1135, 2005.
[25]
W. Zhang and T. Li. Characterizing and mitigating the impact of process variations on phase change based memory systems. In MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pages 2--13, New York, NY, USA, 2009. ACM.
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Published: 24 October 2010
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