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Towards on-chip fault-tolerant communication

Published: 21 January 2003 Publication History

Abstract

As CMOS technology scales down into the deep-submicron (DSM) domain, devices and interconnects are subject to new types of malfunctions and failures that are harder to predict and avoid with the current system-on-chip (SoC) design methodologies. Relaxing the requirement of 100% correctness in operation drastically reduces the costs of design but, at the same time, requires SoCs be designed with some degree of system-level fault-tolerance. In this paper, we introduce a high-level model of DSM failure patterns and propose a new communication paradigm for SoCs, namely stochastic communication. Specifically, for a generic tile-based architecture, we propose a randomized algorithm which not only separates computation from communication, but also provides the required fault-tolerance to on-chip failures. This new technique is easy and cheap to implement in SoCs that integrate a large number of communicating IP cores.

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  • (2016)An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip ArchitecturesACM Transactions on Architecture and Code Optimization10.1145/293067013:2(1-26)Online publication date: 14-Jun-2016
  • (2014)Failure analysis of a network-on-chip for real-time mixed-critical systemsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617010(1-4)Online publication date: 24-Mar-2014
  • (2014)FMEA-based analysis of a Network-on-Chip for mixed-critical systems2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)10.1109/NOCS.2014.7008759(33-40)Online publication date: Sep-2014
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  1. Towards on-chip fault-tolerant communication

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      cover image ACM Conferences
      ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference
      January 2003
      865 pages
      ISBN:0780376609
      DOI:10.1145/1119772
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 21 January 2003

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      Cited By

      View all
      • (2016)An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip ArchitecturesACM Transactions on Architecture and Code Optimization10.1145/293067013:2(1-26)Online publication date: 14-Jun-2016
      • (2014)Failure analysis of a network-on-chip for real-time mixed-critical systemsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617010(1-4)Online publication date: 24-Mar-2014
      • (2014)FMEA-based analysis of a Network-on-Chip for mixed-critical systems2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)10.1109/NOCS.2014.7008759(33-40)Online publication date: Sep-2014
      • (2013)Reliable and adaptive network-on-chip architectures for cyber physical systemsACM Transactions on Embedded Computing Systems10.1145/2435227.243524712:1s(1-21)Online publication date: 21-Mar-2013
      • (2013)Dynamic fault‐tolerant routing algorithm for networks‐on‐chip based on localised detouring pathsIET Computers & Digital Techniques10.1049/iet-cdt.2012.00547:2(93-103)Online publication date: Mar-2013
      • (2013)A NOC closed-loop performance monitor and adapterMicroprocessors & Microsystems10.1016/j.micpro.2011.05.00137:6-7(661-671)Online publication date: 1-Aug-2013
      • (2013)Fault-Tolerant Optimization for Application-Specific Network-on-Chip ArchitectureIAENG Transactions on Engineering Technologies10.1007/978-94-007-6818-5_26(363-381)Online publication date: 12-Sep-2013
      • (2013)Reliable Networks-on-Chip Design for Sustainable Computing SystemsDesign Technologies for Green and Sustainable Computing Systems10.1007/978-1-4614-4975-1_2(23-57)Online publication date: 11-Jun-2013
      • (2012)BibliographyAutonomic Networking-on-Chip10.1201/b11421-10(215-242)Online publication date: 4-Jan-2012
      • (2012)Networks on chips: structure and design methodologiesJournal of Electrical and Computer Engineering10.1155/2012/5094652012(2-2)Online publication date: 1-Jan-2012
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