Article

Hardware verification using ANSI-C programs as a reference

Authors:

Edmund Clarke,

Daniel KroeningAuthors Info & Claims

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Pages 308 - 311

https://doi.org/10.1145/1119772.1119831

Published: 21 January 2003 Publication History

Get Access

Abstract

We describe an algorithm to verify a hardware design given in Verilog using an ANSI-C program as a specification. We use SAT based Bounded Model Checking [1] in order to reduce the equivalence problem to a bit vector logic decision problem. As a case study, we describe experimental results on a hardware and a software implementation of the data encryption standard (DES) algorithm.

References

[1]

A. Biere, A. Cimatti, E. Clarke, and Y. Yhu. Symbolic model checking without BDDs. In Tools and Algorithms for Construction and Analysis of Systems, pages 193--207, 1999.]]

Digital Library

Google Scholar

[2]

C. Pixley. Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits. IEEE Design & Test of Computers, 18(4):4--5, 2001.]]

Digital Library

Google Scholar

[3]

L. Séméria, A. Seawright, R. Mehra, D. Ng, A. Ekanayake, and B. Pangrle. RTL C-based methodology for designing and verifying a multithreaded processor. In Proc. of the 39th Design Automation Conference. ACM Press, 2002.]]

Digital Library

Google Scholar

[4]

http://www.systemc.org.]]

Google Scholar

[5]

A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, and Y. Zhu. Symbolic model checking using SAT procedures instead of BDDs. In Design Automation Conference (DAC'99), 1999.]]

Digital Library

Google Scholar

[6]

International Organization for Standardization. ISO/IEC 9899:1999: Programming languages --- C. International Organization for Standardization, Geneva, Switzerland, 1999.]]

Google Scholar

[7]

M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Proceedings of the 38th Design Automation Conference (DAC'01), June 2001.]]

Digital Library

Google Scholar

Cited By

View all

Bleier NSartori JKumar R(2021)Property-driven Automatic Generation of Reduced-ISA Hardware2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586090(349-354)Online publication date: 5-Dec-2021
https://doi.org/10.1109/DAC18074.2021.9586090
Liew DCadar CDonaldson AStinnett JDumas MPfahl DApel SRusso A(2019)Just fuzz it: solving floating-point constraints using coverage-guided fuzzingProceedings of the 2019 27th ACM Joint Meeting on European Software Engineering Conference and Symposium on the Foundations of Software Engineering10.1145/3338906.3338921(521-532)Online publication date: 12-Aug-2019
https://dl.acm.org/doi/10.1145/3338906.3338921
Leuschner LKüttler MStumpf TBaier CHärtig HKlüppelholz S(2017)Towards Automated Configuration of Systems with Non-Functional ConstraintsProceedings of the 16th Workshop on Hot Topics in Operating Systems10.1145/3102980.3102999(111-117)Online publication date: 7-May-2017
https://dl.acm.org/doi/10.1145/3102980.3102999
Show More Cited By

Recommendations

Hardware Accelerated Functional Verification: Framework for FPGA-Accelerated Functional Verification
Verification of P4 programs in feasible time using assertions
CoNEXT '18: Proceedings of the 14th International Conference on emerging Networking EXperiments and Technologies

Recent trends in software-defined networking have extended network programmability to the data plane. Unfortunately, the chance of introducing bugs increases significantly. Verification can help prevent bugs by assuring that the program does not violate ...
Unbounded safety verification for hardware using software analyzers
DATE '16: Proceedings of the 2016 Conference on Design, Automation & Test in Europe

Demand for scalable hardware verification is ever-increasing. We propose an unbounded safety verification framework for hardware, at the heart of which is a software verifier. To this end, we synthesize Verilog at register transfer level into a software-...

Comments

Information & Contributors

Information

Published In

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

January 2003

865 pages

ISBN:0780376609

DOI:10.1145/1119772

General Chair:
Hiroto Yasuura

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2003

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

56
Total Citations
View Citations
163
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)1

Reflects downloads up to 08 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Bleier NSartori JKumar R(2021)Property-driven Automatic Generation of Reduced-ISA Hardware2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586090(349-354)Online publication date: 5-Dec-2021
https://doi.org/10.1109/DAC18074.2021.9586090
Liew DCadar CDonaldson AStinnett JDumas MPfahl DApel SRusso A(2019)Just fuzz it: solving floating-point constraints using coverage-guided fuzzingProceedings of the 2019 27th ACM Joint Meeting on European Software Engineering Conference and Symposium on the Foundations of Software Engineering10.1145/3338906.3338921(521-532)Online publication date: 12-Aug-2019
https://dl.acm.org/doi/10.1145/3338906.3338921
Leuschner LKüttler MStumpf TBaier CHärtig HKlüppelholz S(2017)Towards Automated Configuration of Systems with Non-Functional ConstraintsProceedings of the 16th Workshop on Hot Topics in Operating Systems10.1145/3102980.3102999(111-117)Online publication date: 7-May-2017
https://dl.acm.org/doi/10.1145/3102980.3102999
Lucanu DRusu VArusoaie A(2017)A generic framework for symbolic executionJournal of Symbolic Computation10.1016/j.jsc.2016.07.01280:P1(125-163)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1016/j.jsc.2016.07.012
Nellen JDriessen KNeuhäußer MÁbrahám EWolters B(2016)Two CEGAR-based approaches for the safety verification of PLC-controlled plantsInformation Systems Frontiers10.1007/s10796-016-9671-918:5(927-952)Online publication date: 11-Jul-2016
https://doi.org/10.1007/s10796-016-9671-9
Mukherjee RJoshi SGriesmayer AKroening DMelham T(2016)Equivalence Checking of a Floating-Point Unit Against a High-Level C ModelFM 2016: Formal Methods10.1007/978-3-319-48989-6_33(551-558)Online publication date: 8-Nov-2016
https://doi.org/10.1007/978-3-319-48989-6_33
Partush NYahav E(2014)Abstract semantic differencing via speculative correlationACM SIGPLAN Notices10.1145/2714064.266024549:10(811-828)Online publication date: 15-Oct-2014
https://dl.acm.org/doi/10.1145/2714064.2660245
Partush NYahav EBlack AMillstein T(2014)Abstract semantic differencing via speculative correlationProceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages & Applications10.1145/2660193.2660245(811-828)Online publication date: 15-Oct-2014
https://dl.acm.org/doi/10.1145/2660193.2660245
Meijer E(2014)The curse of the excluded middleCommunications of the ACM10.1145/260517657:6(50-55)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2605176
Fan WGordon M(2014)The power of social media analyticsCommunications of the ACM10.1145/260257457:6(74-81)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2602574
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Recommendations

Hardware Accelerated Functional Verification: Framework for FPGA-Accelerated Functional Verification

Verification of P4 programs in feasible time using assertions

Unbounded safety verification for hardware using software analyzers

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations