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MAIA: a framework for networks on chip generation and verification

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Ney CalazansAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 49 - 52

https://doi.org/10.1145/1120725.1120741

Published: 18 January 2005 Publication History

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Abstract

The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be developed to integrate NoC interconnection architectures and IP cores into SoCs. Such tools have to fulfill three main requirements: (i) automated NoC generation; (ii) automated production of NoC-IP core interfaces; (iii) seamless analysis of NoC traffic parameters. The objective of this paper is to present the MAIA framework, which includes functions to address all these requirements. NoCs generated by the MAIA framework have been used to successfully prototype SoCs in FPGAs.

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Khamis MEl-Ashry SAbdElsalam MEl-Kharashi MShalaby A(2022)Emulation and verification framework for MPSoC based on NoC and RISC-VDesign Automation for Embedded Systems10.1007/s10617-022-09265-126:3-4(133-159)Online publication date: 14-Sep-2022
https://doi.org/10.1007/s10617-022-09265-1
Aghaei BReshadi MMasdari MSajadi SHosseinzadeh MDarwesh A(2019)Network adapter architectures in network on chip: comprehensive literature reviewCluster Computing10.1007/s10586-019-02924-2Online publication date: 15-Mar-2019
https://doi.org/10.1007/s10586-019-02924-2
Aghaei BKhademzadeh AReshadi MBadie K(2017)Link TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5646-033:2(209-225)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s10836-017-5646-0
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Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 18 January 2005

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ASPDAC05

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

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Khamis MEl-Ashry SAbdElsalam MEl-Kharashi MShalaby A(2022)Emulation and verification framework for MPSoC based on NoC and RISC-VDesign Automation for Embedded Systems10.1007/s10617-022-09265-126:3-4(133-159)Online publication date: 14-Sep-2022
https://doi.org/10.1007/s10617-022-09265-1
Aghaei BReshadi MMasdari MSajadi SHosseinzadeh MDarwesh A(2019)Network adapter architectures in network on chip: comprehensive literature reviewCluster Computing10.1007/s10586-019-02924-2Online publication date: 15-Mar-2019
https://doi.org/10.1007/s10586-019-02924-2
Aghaei BKhademzadeh AReshadi MBadie K(2017)Link TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5646-033:2(209-225)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s10836-017-5646-0
Gogte VLee DParikh RBertacco VEbrahimi MLocatelli R(2015)NoCVisionProceedings of the 8th International Workshop on Network on Chip Architectures10.1145/2835512.2835518(21-26)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2835512.2835518
Ogras UMarculescu ROgras UMarculescu R(2013)Literature SurveyModeling, Analysis and Optimization of Network-on-Chip Communication Architectures10.1007/978-94-007-3958-1_2(9-32)Online publication date: 13-Mar-2013
https://doi.org/10.1007/978-94-007-3958-1_2
(2012)BibliographyAutonomic Networking-on-Chip10.1201/b11421-10(215-242)Online publication date: 4-Jan-2012
https://doi.org/10.1201/b11421-10
Heck GGuazzelli RMoraes FCalazans NSoares R(2012)HardNoC: A platform to validate networks on chip through FPGA prototyping2012 VIII Southern Conference on Programmable Logic10.1109/SPL.2012.6211781(1-6)Online publication date: Mar-2012
https://doi.org/10.1109/SPL.2012.6211781
Marcon CCalazans NMoreno EMoraes FHessel FSusin A(2011)CAFESJournal of Parallel and Distributed Computing10.1016/j.jpdc.2010.10.00271:5(714-728)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1016/j.jpdc.2010.10.002
Kornaros G(2010)NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnectsInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2010.0345392:3/4(177-186)Online publication date: 1-Aug-2010
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Sehgal VChauhan D(2010)State observer controller design for packets flow control in networks-on-chipThe Journal of Supercomputing10.1007/s11227-009-0322-554:3(298-329)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1007/s11227-009-0322-5
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PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

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