Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/1140389.1140391acmconferencesArticle/Chapter ViewAbstractPublication PagesscopesConference Proceedingsconference-collections
Article

Performance guarantees by simulation of process

Published: 29 September 2005 Publication History
  • Get Citation Alerts
  • Abstract

    In this paper we derive the end-to-end temporal behavior of real-time applications that are described as process networks. We demonstrate that a tight upper bound on the arrival time of data can be derived by simulation of this process network. We also show that the effects of arbitration can be taken into account if resources are reserved. For an H263 video decoder example we derive by means of simulation the settings of the schedulers and the buffer capacities. We arrive at the conclusion that for this application a close to maximum throughput is obtained with small buffers if only one process is executed on each processor. Larger buffers are needed if processors are shared and processes are executed during long time-slices.

    References

    [1]
    E. A Kock, G. Essink, W. J. M. Smits, P. van der Wolf, J.-Y. Brunel, W. M. Kruijtzer, P. Lieverse, and K. A. Vissers, "YAPI: Application modeling for signal processing systems", in Proc. Design Automation Conference (DAC), Los Angeles, June 2000, pp. 402--405.
    [2]
    G. Kahn, "The semantics of a simple language for parallel programming", in Proceedings IFIP Congress, 1974, pp. 471--475.
    [3]
    A. Donlin, "Transaction level modeling: Flows and use models", in Proc. Int'l Symposium on Hardware/Software Codesign (CODES), 2004, pp. 75--80.
    [4]
    D. E. Culler, H. P. Singh, and A. Gupta, Parallel Computer Architecture: a hardware/software approach, Morgan Kaufmann, 1999.
    [5]
    E. Rijpkema, K. G. W. Goossens, A. Rǎdulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander, "Tradeoffs in the design of a router with both guaranteed and best-effort services for networks on chip", in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2003, pp. 350--355.
    [6]
    M. Bekooij, O. Moreira, P. Poplavko, B. Mesman, M. Pastrnak, and J. van Meerbergen, "Predictable embedded multiprocessor system design", in Proc. Int'l Workshop on Software and Compilers for Embedded Systems (SCOPES). Sept. 2004, LNCS 3199, Springer.
    [7]
    C. W. Mercer, S. Savage, and H. Tokuda, "Processor capacity reserves: Operating system support for multimedia systems", in Proc. IEEE International Conference of Multimedia Computing and Systems. IEEE Computer Society Press, 1994.
    [8]
    H. Zhang, "Service disciplines for guaranteed performance services in packet-switching networks", Proceedings of the IEEE, vol. 83, no. 10, pp. 1374--96, October 1995.
    [9]
    E. A. Lee and T. M. Parks, "Dataflow process networks", in Proceedings of the IEEE, May 1995.
    [10]
    A. D. Pimentel, L. O. Hertzberger, P. Lieverse, P. van der Wolf, and E. F. Deprettere, "Explorating embedded-systems architectures with Artemis", IEEE Computer, vol. 34, no. 11, pp. 57--63, 2001.
    [11]
    K. Lahiri, A. Raghunathan, and S. Dey, "Fast performance analysis of bus-base system-on-chip communication architectures", in Proc. of Int'l Conference on Computer Aided Design (ICCAD), 1999, pp. 566--572.
    [12]
    J-Y. Brunel, W. M. Kruijtzer, H. J. H. N. Kenter, F. Pétrot, L. Pasquier, E. A. de Kock, and W. J. M. Smits, "COSY communication IP's", in Proc. Design Automation Conference (DAC), 2000, pp. 406--409.
    [13]
    A. Maxiaguine, Y. Zhu, S. Chakraborty, and W. Wong, "Tuning SoC platforms for multimedia processing: Identifying limits and tradeoffs", in Proc. Int'l Symposium on Hardware/Software Codesign (CODES), 2004, pp. 128--133.
    [14]
    D. Kang, G. Richard, and M. Saksena, "Performance-based design of distributed real-time systems", in Proc. Euromicro Conference on Real-Time Systems, 1997, pp. 2--13.
    [15]
    E. A. Lee and D. G. Messerschmitt, "Synchronous data flow", in Proceedings of the IEEE, 1987.
    [16]
    S. Sriram and S. S. Bhattacharyya, Embedded Multiprocessors: Scheduling and Synchronization, Marcel Dekker Inc., 2000.
    [17]
    P. Poplavko, T. Basten, M. Bekooij, J. van Meerbergen, and B. Mesman, "Task-level timing models for guaranteed performance in multiprocessor networks-on-chip", in Proc. Int'l Conf. on Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2003, pp. 63--72.
    [18]
    O. P. Gangwal, A. Nieuwland, and P. Lippens, "A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems", in Int'l Symposium on System Synthesis (ISSS). 2001, pp. 1--6, ACM.
    [19]
    A. Moonen, M. Bekooij, and J. van Meerbergen, "Timing analysis model for network based multiprocessor systems", in Proc. Workshop of Circuits, System and Signal Processing (ProRISC), Veldhoven, The Netherlands, 2004, pp. 91--99.

    Cited By

    View all
    • (2016)HAPIProceedings of the 19th International Workshop on Software and Compilers for Embedded Systems10.1145/2906363.2906381(60-66)Online publication date: 23-May-2016
    • (2016)Compositional Temporal Analysis Method for Fixed Priority Pre-emptive Scheduled Modal Stream Processing ApplicationsProceedings of the 19th International Workshop on Software and Compilers for Embedded Systems10.1145/2906363.2906375(98-107)Online publication date: 23-May-2016
    • (2016)Combining Offsets with Precedence Constraints to Improve Temporal Analysis of Cyclic Real-Time Streaming Applications2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS.2016.7461325(1-12)Online publication date: Apr-2016
    • Show More Cited By
    1. Performance guarantees by simulation of process

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      SCOPES '05: Proceedings of the 2005 workshop on Software and compilers for embedded systems
      September 2005
      132 pages
      ISBN:1595932070
      DOI:10.1145/1140389
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 29 September 2005

      Permissions

      Request permissions for this article.

      Check for updates

      Qualifiers

      • Article

      Acceptance Rates

      Overall Acceptance Rate 38 of 79 submissions, 48%

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)2
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 29 Jul 2024

      Other Metrics

      Citations

      Cited By

      View all
      • (2016)HAPIProceedings of the 19th International Workshop on Software and Compilers for Embedded Systems10.1145/2906363.2906381(60-66)Online publication date: 23-May-2016
      • (2016)Compositional Temporal Analysis Method for Fixed Priority Pre-emptive Scheduled Modal Stream Processing ApplicationsProceedings of the 19th International Workshop on Software and Compilers for Embedded Systems10.1145/2906363.2906375(98-107)Online publication date: 23-May-2016
      • (2016)Combining Offsets with Precedence Constraints to Improve Temporal Analysis of Cyclic Real-Time Streaming Applications2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS.2016.7461325(1-12)Online publication date: Apr-2016
      • (2011)Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority ArbitrationProceedings of the 2011 IEEE17th International Conference on Embedded and Real-Time Computing Systems and Applications - Volume 0110.1109/RTCSA.2011.54(309-318)Online publication date: 28-Aug-2011
      • (2011)Related WorkMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_4(49-54)Online publication date: 10-Jan-2011
      • (2011)Principles of Design Space ExplorationMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_3(23-47)Online publication date: 10-Jan-2011
      • (2009)Monotonicity and run-time schedulingProceedings of the seventh ACM international conference on Embedded software10.1145/1629335.1629359(177-186)Online publication date: 12-Oct-2009
      • (2009)Composable Resource Sharing Based on Latency-Rate ServersProceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools10.1109/DSD.2009.167(547-555)Online publication date: 27-Aug-2009
      • (2009)A Priority-Based Budget Scheduler with Conservative Dataflow ModelProceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools10.1109/DSD.2009.148(37-44)Online publication date: 27-Aug-2009
      • (2007)Modelling run-time arbitration by latency-rate servers in dataflow graphsProceedingsof the 10th international workshop on Software & compilers for embedded systems10.1145/1269843.1269846(11-22)Online publication date: 20-Apr-2007
      • Show More Cited By

      View Options

      Get Access

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media