Article

Area and performance optimization of a generic network-on-chip architecture

Authors:

Mário P. Véstias,

Horácio C. NetoAuthors Info & Claims

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

Pages 68 - 73

https://doi.org/10.1145/1150343.1150365

Published: 28 August 2006 Publication History

Abstract

Complex Systems-on-Chip (SoC) with multiple interconnected stand-alone designs require high scalability and bandwidth. Network-on-Chip (NoC) is a scalable communication infrastructure able to tackle the communication needs of these SoCs. In this paper, we consider the optimization of a generic NoC to improve area and performance of NoC based architectures for dedicated applications. The generic NoC can be tailored to an application by changing the number of routers, by configuring each router to specific traffic requirements, and by choosing the set of links between routers and cores. The optimization algorithm determines the appropriate NoC and routers configuration to support a set of applications considering the optimization of area, and performance. The final solution will consist of an heterogeneous NoC with improved quality. The approach has been tested under different operating conditions assuming implementations on an FPGA.

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Cited By

Peng JAlkabani YFavry EMehrabian ASun SSorger VEl-Ghazawi T(2023)Adaptive Routing for Hybrid Photonic–Plasmonic (HyPPI) Interconnection Network for Manycore Processors Using DDDAS on the ChipHandbook of Dynamic Data Driven Applications Systems10.1007/978-3-031-27986-7_34(903-925)Online publication date: 6-Sep-2023
https://doi.org/10.1007/978-3-031-27986-7_34
Narayanasamy PMuthurathinam SGopoalakrishnan SArslan TSudarsan S(2018)R3ToS based Partially Reconfigurable Data Flow Pipelined Network on chip2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)10.1109/AHS.2018.8541478(210-213)Online publication date: Aug-2018
https://doi.org/10.1109/AHS.2018.8541478
Diao XLi HTan WGu H(2018)Increasing Communication Path Diversity in Mesh-Based ONoC by Using Multi-Interface Processing Cores2018 Asia Communications and Photonics Conference (ACP)10.1109/ACP.2018.8595880(1-3)Online publication date: Oct-2018
https://doi.org/10.1109/ACP.2018.8595880
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Index Terms

Area and performance optimization of a generic network-on-chip architecture
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links

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Published In

cover image ACM Conferences

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

August 2006

248 pages

ISBN:1595934790

DOI:10.1145/1150343

General Chair:
Claudionor Coelho
Universidade de Minas Gerais, Brazil
,
Program Chairs:
Ricardo Jacobi
Universidade de Brasilia, Brazil
,
Juergen Becker
Universitaet Karlsruhe (TH), Germany

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 28 August 2006

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SBCCI06

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SBCCI06: 19th Symposium on Integrated Circuits and System Design

August 28 - September 1, 2006

MG, Ouro Preto, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Peng JAlkabani YFavry EMehrabian ASun SSorger VEl-Ghazawi T(2023)Adaptive Routing for Hybrid Photonic–Plasmonic (HyPPI) Interconnection Network for Manycore Processors Using DDDAS on the ChipHandbook of Dynamic Data Driven Applications Systems10.1007/978-3-031-27986-7_34(903-925)Online publication date: 6-Sep-2023
https://doi.org/10.1007/978-3-031-27986-7_34
Narayanasamy PMuthurathinam SGopoalakrishnan SArslan TSudarsan S(2018)R3ToS based Partially Reconfigurable Data Flow Pipelined Network on chip2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)10.1109/AHS.2018.8541478(210-213)Online publication date: Aug-2018
https://doi.org/10.1109/AHS.2018.8541478
Diao XLi HTan WGu H(2018)Increasing Communication Path Diversity in Mesh-Based ONoC by Using Multi-Interface Processing Cores2018 Asia Communications and Photonics Conference (ACP)10.1109/ACP.2018.8595880(1-3)Online publication date: Oct-2018
https://doi.org/10.1109/ACP.2018.8595880
Amagasaki MMurase FKuga MIida MSueyoshi T(2017)FPGA based ASIC Emulator with High Speed Optical Serial LinksProceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3120895.3120913(1-6)Online publication date: 7-Jun-2017
https://dl.acm.org/doi/10.1145/3120895.3120913
Ben-Itzhak YCidon IKolodny AShabun MShmuel N(2015)Heterogeneous NoC Router ArchitectureIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2014.235181626:9(2479-2492)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1109/TPDS.2014.2351816
Brugge MKhalid M(2014)A Parameterizable NoC Router for FPGAsJournal of Computers10.4304/jcp.9.3.519-5289:3Online publication date: 1-Mar-2014
https://doi.org/10.4304/jcp.9.3.519-528
Oommen DPradeep C(2012)Reconfigurable router using RLBS algorithm2012 12th International Conference on Intelligent Systems Design and Applications (ISDA)10.1109/ISDA.2012.6416560(332-336)Online publication date: Nov-2012
https://doi.org/10.1109/ISDA.2012.6416560
Matos DConcatto CCarro L(2012)Reconfigurable Intercommunication Infrastructure: NoCsAdaptable Embedded Systems10.1007/978-1-4614-1746-0_5(119-161)Online publication date: 20-Oct-2012
https://doi.org/10.1007/978-1-4614-1746-0_5
Matos DConcatto CKreutz MKastensmidt FCarro LSusin A(2011)Reconfigurable Routers for Low Power and High PerformanceIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.206806419:11(2045-2057)Online publication date: 1-Nov-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2068064
Shi QHu W(2011)Hybrid on-chip interconnection with coupled cores in tiles2011 International Conference on Electronics, Communications and Control (ICECC)10.1109/ICECC.2011.6066624(274-277)Online publication date: Sep-2011
https://doi.org/10.1109/ICECC.2011.6066624
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