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Strategies for achieving improved processor throughput

Authors:

Matthew K. Farrens,

Andrew R. PleszkunAuthors Info & Claims

ISCA '91: Proceedings of the 18th annual international symposium on Computer architecture

Pages 362 - 369

https://doi.org/10.1145/115952.115988

Published: 01 April 1991 Publication History

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Cited By

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Hamdioui SKvatinsky SCauwenberghs GXie LWald NJoshi SElsayed HCorporaal HBertels K(2017)Memristor for computingProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130553(722-731)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130553
Hamdioui SKvatinsky SCauwenberghs GXie LWald NJoshi SElsayed HCorporaal HBertels K(2017)Memristor for computing: Myth or reality?Design, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927083(722-731)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927083
Patel RKvatinsky SFriedman EKolodny A(2015)Multistate Register Based on Resistive RAMIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.234792623:9(1750-1759)Online publication date: Sep-2015
https://doi.org/10.1109/TVLSI.2014.2347926
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Index Terms

Strategies for achieving improved processor throughput
1. Computer systems organization
  1. Architectures
    1. Serial architectures
      1. Pipeline computing
2. General and reference
  1. Cross-computing tools and techniques
    1. Performance

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Published In

ISCA '91: Proceedings of the 18th annual international symposium on Computer architecture

April 1991

399 pages

ISBN:0897913949

DOI:10.1145/115952

Chairman:
Zvonko Vranesic

ACM SIGARCH Computer Architecture News Volume 19, Issue 3
Special Issue: Proceedings of the 18th annual international symposium on Computer architecture (ISCA '91)
May 1991
375 pages
ISSN:0163-5964
DOI:10.1145/115953
Editor:
Zvonko Vranesic
Univ. of Toronto, Toronto, Canada
Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1991

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ISCA91

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SIGARCH
IEEE-CS

ISCA91: 18th International Symposium on Computer Architecture

May 27 - 30, 1991

Ontario, Toronto, Canada

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

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Hamdioui SKvatinsky SCauwenberghs GXie LWald NJoshi SElsayed HCorporaal HBertels K(2017)Memristor for computingProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130553(722-731)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130553
Hamdioui SKvatinsky SCauwenberghs GXie LWald NJoshi SElsayed HCorporaal HBertels K(2017)Memristor for computing: Myth or reality?Design, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927083(722-731)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927083
Patel RKvatinsky SFriedman EKolodny A(2015)Multistate Register Based on Resistive RAMIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.234792623:9(1750-1759)Online publication date: Sep-2015
https://doi.org/10.1109/TVLSI.2014.2347926
Kvatinsky SNacson YEtsion YFriedman EKolodny AWeiser U(2014)Memristor-Based MultithreadingIEEE Computer Architecture Letters10.1109/L-CA.2013.313:1(41-44)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1109/L-CA.2013.3
Gabor RMendelson AWeiss S(2009)Service level agreement for multithreaded processorsACM Transactions on Architecture and Code Optimization10.1145/1543753.15437556:2(1-33)Online publication date: 6-Jul-2009
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Gabor RWeiss SMendelson A(2007)Fairness enforcement in switch on event multithreadingACM Transactions on Architecture and Code Optimization10.1145/1275937.12759394:3(15-es)Online publication date: 1-Sep-2007
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Gabor RWeiss SMendelson A(2006)Fairness and Throughput in Switch on Event MultithreadingProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2006.25(149-160)Online publication date: 9-Dec-2006
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Eickemeyer RJohnson RKunkel SLime BSquillante MWu C(2005)Evaluation of multithreaded processors and thread-switch policiesHigh Performance Computing10.1007/BFb0024207(75-90)Online publication date: 9-Jun-2005
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Wang PCollins JWang HKim DGreene BChan KYunus ASych TMoore SShen J(2004)Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platformACM SIGOPS Operating Systems Review10.1145/1037949.102441138:5(144-155)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1037949.1024411
Wang PCollins JWang HKim DGreene BChan KYunus ASych TMoore SShen J(2004)Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platformACM SIGARCH Computer Architecture News10.1145/1037947.102441132:5(144-155)Online publication date: 7-Oct-2004
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