Article

A buffered crossbar-based chip interconnection framework supporting quality of service

Authors:

Ioannis Papaefstathiou,

George Kornaros,

Nikolaos ChrysosAuthors Info & Claims

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

Pages 90 - 95

https://doi.org/10.1145/1228784.1228810

Published: 11 March 2007 Publication History

Abstract

As Systems-on-a-Chip (SoCs) become larger, the problem of interconnecting the various subsystems becomes more complicated. In this framework, certain alternatives to the standard buses, based on Network Technologies, have emerged as innovative approaches for SoC's interconnect. One of the main advantages of such an alternative, is that it can offer certain Quality of Service (QoS) over the internal cross-connects while at the same time it supports higher transfer rates than the existing on-chip buses. This paper presents the first chip interconnection architecture, which is based on a buffered crossbar switch. The main advantage of the proposed system is that it efficiently supports different priority levels; it also provides several Gigabits per Second of aggregate bandwidth, while it introduces very low latency. Moreover, the hardware complexity of this highly scalable scheme is minimal. All those facts make this framework ideal for SoCs that contain IP cores with diverse speed/throughput requirements.

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Cited By

Pan DMakki KPissinou N(2010)Achieve constant performance guarantees using asynchronous crossbar scheduling without speedup2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)10.1109/IPDPS.2010.5470456(1-12)Online publication date: Apr-2010
https://doi.org/10.1109/IPDPS.2010.5470456
Karimi MSun ZPan DChen Z(2009)Packet-mode asynchronous scheduling algorithm for partially buffered crossbar switchesProceedings of the 28th IEEE conference on Global telecommunications10.5555/1811982.1812234(5144-5149)Online publication date: 30-Nov-2009
https://dl.acm.org/doi/10.5555/1811982.1812234
Pan DMakki KPissinou N(2009)Fair queueing based packet scheduling for buffered crossbar switchesProceedings of the 28th IEEE conference on Global telecommunications10.5555/1811380.1811644(1592-1597)Online publication date: 30-Nov-2009
https://dl.acm.org/doi/10.5555/1811380.1811644
Show More Cited By

Index Terms

A buffered crossbar-based chip interconnection framework supporting quality of service
1. Hardware
  1. Integrated circuits
    1. Interconnect
      1. Input / output circuits

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cover image ACM Conferences

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

March 2007

626 pages

ISBN:9781595936059

DOI:10.1145/1228784

General Chairs:
Hai Zhou
Northwestern University
,
Enrico Macii
Politecnico di Torino
,
Program Chairs:
Zhiyuan Yan
Lehigh University
,
Yehia Massoud
Rice University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 March 2007

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March 11 - 13, 2007

Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Pan DMakki KPissinou N(2010)Achieve constant performance guarantees using asynchronous crossbar scheduling without speedup2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)10.1109/IPDPS.2010.5470456(1-12)Online publication date: Apr-2010
https://doi.org/10.1109/IPDPS.2010.5470456
Karimi MSun ZPan DChen Z(2009)Packet-mode asynchronous scheduling algorithm for partially buffered crossbar switchesProceedings of the 28th IEEE conference on Global telecommunications10.5555/1811982.1812234(5144-5149)Online publication date: 30-Nov-2009
https://dl.acm.org/doi/10.5555/1811982.1812234
Pan DMakki KPissinou N(2009)Fair queueing based packet scheduling for buffered crossbar switchesProceedings of the 28th IEEE conference on Global telecommunications10.5555/1811380.1811644(1592-1597)Online publication date: 30-Nov-2009
https://dl.acm.org/doi/10.5555/1811380.1811644
Pan DMakki KPissinou N(2009)Fair Queueing Based Packet Scheduling for Buffered Crossbar SwitchesGLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference10.1109/GLOCOM.2009.5425680(1-6)Online publication date: Nov-2009
https://doi.org/10.1109/GLOCOM.2009.5425680
Karimi MSun ZPan DChen Z(2009)Packet-Mode Asynchronous Scheduling Algorithm for Partially Buffered Crossbar SwitchesGLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference10.1109/GLOCOM.2009.5425406(1-6)Online publication date: Nov-2009
https://doi.org/10.1109/GLOCOM.2009.5425406

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