Article

Express virtual channels: towards the ideal interconnection fabric

Authors:

Niraj K. JhaAuthors Info & Claims

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

Pages 150 - 161

https://doi.org/10.1145/1250662.1250681

Published: 09 June 2007 Publication History

Abstract

Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the pervasive communication fabric to connect different processing elements in many-core chips. However, current state-of-the-art packet-switched networks rely on complex routers which increases the communication overhead and energy consumption as compared to the ideal interconnection fabric.

In this paper, we try to close the gap between the state-of-the-art packet-switched network and the ideal interconnect by proposing express virtual channels (EVCs), a novel flow control mechanism which allows packets to virtually bypass intermediate routers along their path in a completely non-speculative fashion, thereby lowering the energy/delay towards that of a dedicated wire while simultaneously approaching ideal throughput with a practical design suitable for on-chip networks.

Our evaluation results using a detailed cycle-accurate simulator on a range of synthetic traffic and SPLASH benchmark traces show upto 84% reduction in packet latency and upto 23% improvement in throughput while reducing the average router energy consumption by upto 38% over an existing state-of-the-art packet-switched design. When compared to the ideal interconnect, EVCs add just two cycles to the no-load latency, and are within 14% of the ideal throughput. Moreover, we show that the proposed design incurs a minimal hardware overhead while exhibiting excellent scalability with increasing network sizes.

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Yin LGhazizadeh ALouri AZheng H(2023)ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323955(1-9)Online publication date: 28-Oct-2023
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Index Terms

Express virtual channels: towards the ideal interconnection fabric
1. Networks
  1. Network types
    1. Packet-switching networks

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cover image ACM Conferences

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

June 2007

542 pages

ISBN:9781595937063

DOI:10.1145/1250662

General Chair:
Dean Tullsen
University of California, San Diego
,
Program Chair:
Brad Calder
Microsoft & University of California, San Diego

ACM SIGARCH Computer Architecture News Volume 35, Issue 2
May 2007
527 pages
ISSN:0163-5964
DOI:10.1145/1273440
Issue’s Table of Contents

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 09 June 2007

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SPAA07: 19th ACM Symposium on Parallelism in Algorithms and Architectures

June 9 - 13, 2007

California, San Diego, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

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https://doi.org/10.37391/ijeer.110130
Yin LGhazizadeh ALouri AZheng H(2023)ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323955(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323955
Zheng HLouri A(2022)Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip DesignIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.300349610:1(223-236)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TETC.2020.3003496
Luo YDutta SKaul ALim SBakir MDatta SYu S(2022)A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable InterconnectIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2022.317757712:2(445-457)Online publication date: Jun-2022
https://doi.org/10.1109/JETCAS.2022.3177577
Farrokhbakht HGratz PKrishna TMiguel JEnright Jerger N(2022)Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00074(957-970)Online publication date: Apr-2022
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Jiao JHe YCao TKondo M(2022)Enabling circuit-switching in modern on-chip networksMicroprocessors and Microsystems10.1016/j.micpro.2022.10471295(104712)Online publication date: Nov-2022
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Zhou WOuyang YLu YLiang H(2022)A router architecture with dual input and dual output channels for Networks-on-ChipMicroprocessors & Microsystems10.1016/j.micpro.2022.10446490:COnline publication date: 1-Apr-2022
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Monemi APérez ILeyva NVallejo EBeivide RMoretó MKrishna TKim JAbadal SMiguel J(2021)PIugSMARTProceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip10.1145/3479876.3481601(41-48)Online publication date: 14-Oct-2021
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Li YLouri A(2021)ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore ArchitecturesIEEE Transactions on Sustainable Computing10.1109/TSUSC.2020.29813406:2(274-288)Online publication date: 1-Apr-2021
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Perez IVallejo EBeivide R(2021)S-SMART++: A Low-Latency NoC Leveraging Speculative Bypass RequestsIEEE Transactions on Computers10.1109/TC.2021.306861570:6(819-832)Online publication date: 1-Jun-2021
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