Article

Sketching stencils

Authors:

Armando Solar-Lezama,

Rastislav Bodik,

Vijay Saraswat,

Sanjit SeshiaAuthors Info & Claims

PLDI '07: Proceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation

Pages 167 - 178

https://doi.org/10.1145/1250734.1250754

Published: 10 June 2007 Publication History

Abstract

Performance of stencil computations can be significantly improved through smart implementations that improve memory locality, computation reuse, or parallelize the computation. Unfortunately, efficient implementations are hard to obtain because they often involve non-traditional transformations, which means that they cannot be produced by optimizing the reference stencil with a compiler. In fact, many stencils are produced by code generators that were tediously handcrafted.

In this paper, we show how stencil implementations can be produced with sketching. Sketching is a software synthesis approach where the programmer develops a partial implementation--a sketch--and a separate specification of the desired functionality given by a reference (unoptimized) stencil. The synthesizer then completes the sketch to behave like the specification, filling in code fragments that are difficult to develop manually.

Existing sketching systems work only for small finite programs, i.e.,, programs that can be represented as small Boolean circuits. In this paper, we develop a sketching synthesizer that works for stencil computations, a large class of programs that, unlike circuits, have unbounded inputs and outputs, as well as an unbounded number of computations. The key contribution is a reduction algorithm that turns a stencil into a circuit, allowing us to synthesize stencils using an existing sketching synthesizer.

References

[1]

W. Ackermann. Solvable cases of the decision problem. Studies in Logic and the Foundations. of Mathematics. North Ü Holland, 1954.

[2]

D. H. Bailey, E. Barszcz, J. T. Barton, D. S. Browning, R. L. Carter, D. Dagum, R. A. Fatoohi, P. O. Frederickson, T. A. Lasinski, R. S. Schreiber, H. D. Simon, V. Venkatakrishnan, and S. K. Weeratunga. The nas parallel benchmarks. The International Journal of Supercomputer Applications, 5(3):63--73, Fall 1991.

Digital Library

[3]

W. L. Briggs, V. E. Henson, and S. F. McCormick. A Multigrid Tutorial. SIAM, 2000.

Digital Library

[4]

R. E. Bryant, S. German, and M. N. Velev. Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic. ACM Transactions on Computational Logic, 2(1):1--41, January 2001.

Digital Library

[5]

R. E. Bryant, D. Kroening, J. Ouaknine, S. A. Seshia, O. Strichman, and B. Brady. Deciding bit-vector arithmetic with abstraction. In Proc. TACAS 2007, March 2007.

Digital Library

[6]

D. Currie, X. Feng, M. Fujita, A. J. Hu, M. Kwan, and S. Rajan. Embedded software verification using symbolic execution and uninterpreted functions. Int. J. Parallel Program., 34(1):61--91, 2006.

Digital Library

[7]

J. Demmel, J. Dongarra, V. Eijkhout, E. Fuentes, A. Petitet, R. Vuduc, C. Whaley, and K. Yelick. Self adapting linear algebra algorithms and software. Proceedings of the IEEE, 93(2), 2005.

[8]

C. C. Douglas, J. Hu, M. Kowarschik, U. Rüde, and C. Weiss. Cache optimization for structured and unstructured grid multigrid. Elect. Trans. Numer. Anal., 10:21--40, 2000.

[9]

M. Frigo and S. Johnson. Fftw: An adaptive software architecture for the fft. In ICASSP conference proceedings, volume 3, pages 1381--1384, 1998.

[10]

M. Frigo and V. Strumpen. The memory behavior of cache oblivious stencil computations. The Journal of Supercomputing, 39(2):93--112, 2007.

Digital Library

[11]

S. Kamil, K. Datta, S. Williams, L. Oliker, J. Shalf, and K. Yelick. Implicit and explicit optimizations for stencil computations. In MSPC '06: Proceedings of the 2006 workshop on Memory system performance and correctness, pages 51--60, New York, NY, USA, 2006. ACM Press.

Digital Library

[12]

S. Kamil, P. Husbands, L. Oliker, J. Shalf, and K. A. Yelick. Impact of modern memory subsystems on cache optimizations for stencil computations. In B. Calder and B. G. Zorn, editors, Memory System Performance, pages 36--43. ACM, 2005.

Digital Library

[13]

K. McMillan. Verification of infinite state systems by compositional model checking. In Correct Hardware Design and Verification Methods: 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 1999., pages 219--237, 1999.

Digital Library

[14]

A. Mishchenko, S. Chatterjee, and R. Brayton. Dag-aware AIG rewriting: A fresh look at combinational logic synthesis. In DAC '06: Proceedings of the 43rd annual conference on Design automation, pages 532--535, New York, NY, USA, 2006. ACM Press.

Digital Library

[15]

A. Pnueli, O. Shtrichman, and M. Siegel. The code validation tool (cvt). International Journal on Software Tools for Technology Transfer (STTT), 2, December 1998.

[16]

W. Pugh. The omega test: a fast and practical integer programming algorithm for dependence analysis. In Supercomputing '91: Proceedings of the 1991 ACM/IEEE conference on Supercomputing, pages 4--13, New York, NY, USA, 1991. ACM Press.

Digital Library

[17]

M. Püschel, B. Singer, J. Xiong, J. Moura, J. Johnson, D. Padua, M. Veloso, and R. Johnson. Spiral: A generator for platform-adapted libraries of signal processing algorithms. Journal of High Performance Computing and Applications, accepted for publication.

Digital Library

[18]

G. Roth, J. Mellor-Crummey, K. Kennedy, and R. G. Brickner. Compiling stencils in high performance fortran. In Supercomputing '97: Proceedings of the 1997 ACM/IEEE conference on Supercomputing (CDROM), pages 1--20, New York, NY, USA, 1997. ACM Press.

Digital Library

[19]

S. Sellappa and S. Chatterjee. Cache-efficient multigrid algorithms. Int. J. High Perform. Comput. Appl., 18(1):115--133, 2004.

Digital Library

[20]

L. Snyder. Programming Guide to ZPL. MIT Press, Cambridge, MA, 1999.

Digital Library

[21]

A. Solar-Lezama, L. Tancau, R. Bodik, V. Saraswat, and S. Seshia. Combinatorial sketching for finite programs. In 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2006), pages 404--415, New York, NY, USA, 2006. ACM Press.

Digital Library

[22]

A. Solar-Lezama, L. Tancau, R. Bodik, V. Saraswat, and S. Seshia. Combinatorial sketching for finite programs. In ASPLOS '06,San Jose, CA, USA, 2006. ACM Press.

Digital Library

[23]

D. Wonnacott. Achieving scalable locality with time skewing. International Journal of Parallel Programming, 30(3):1--221, 2002.

Digital Library

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Index Terms

Sketching stencils
1. Software and its engineering
  1. Software creation and management
    1. Designing software
      1. Software implementation planning
        Software design techniques
    2. Software development process management
  2. Software notations and tools
    1. General programming languages
      1. Language features

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Published In

cover image ACM Conferences

PLDI '07: Proceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation

June 2007

508 pages

ISBN:9781595936332

DOI:10.1145/1250734

General Chair:
Jeanne Ferrante
University of California, San Diego, USA
,
Program Chair:
Kathryn S. McKinley
University of Texas at Austin, USA

ACM SIGPLAN Notices Volume 42, Issue 6
Proceedings of the 2007 PLDI conference
June 2007
491 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1273442
Issue’s Table of Contents

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 10 June 2007

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PLDI '07

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PLDI '07: ACM SIGPLAN Conference on Programming Language Design and Implementation

June 10 - 13, 2007

California, San Diego, USA

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Overall Acceptance Rate 406 of 2,067 submissions, 20%

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Patton NRahmani KMissula MBiswas JDillig I(2024)Programming-by-Demonstration for Long-Horizon Robot TasksProceedings of the ACM on Programming Languages10.1145/36328608:POPL(512-545)Online publication date: 5-Jan-2024
https://doi.org/10.1145/3632860
Segovia-Aguas JJiménez SJonsson A(2024)Generalized Planning as Heuristic Search: A new planning search-space that leverages pointers over objectsArtificial Intelligence10.1016/j.artint.2024.104097(104097)Online publication date: Feb-2024
https://doi.org/10.1016/j.artint.2024.104097
Fleischer MDas DBose PBai WLu KPayer MKruegel CVigna GCalandrino JTroncoso C(2023)ACTORProceedings of the 32nd USENIX Conference on Security Symposium10.5555/3620237.3620517(5003-5020)Online publication date: 9-Aug-2023
https://dl.acm.org/doi/10.5555/3620237.3620517
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https://doi.org/10.1007/s10703-023-00417-y
Murali APeña LBlanchard ELöding CMadhusudan P(2022)Model-guided synthesis of inductive lemmas for FOL with least fixpointsProceedings of the ACM on Programming Languages10.1145/35633546:OOPSLA2(1873-1902)Online publication date: 31-Oct-2022
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Mariano BChen YFeng YDurrett GDillig I(2022)Automated transpilation of imperative to functional code using neural-guided program synthesisProceedings of the ACM on Programming Languages10.1145/35273156:OOPSLA1(1-27)Online publication date: 29-Apr-2022
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Nguyen TYadavally ANguyen T(2022)Phrase2Set: Phrase-to-Set Machine Translation and Its Software Engineering Applications2022 IEEE International Conference on Software Analysis, Evolution and Reengineering (SANER)10.1109/SANER53432.2022.00068(502-513)Online publication date: Mar-2022
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Xu XWang XXue J(2021)Automatic Synthesis of Data-Flow AnalyzersStatic Analysis10.1007/978-3-030-88806-0_22(453-478)Online publication date: 13-Oct-2021
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Farzan ANicolet V(2021)Counterexample-Guided Partial Bounding for Recursive Function SynthesisComputer Aided Verification10.1007/978-3-030-81685-8_39(832-855)Online publication date: 15-Jul-2021
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