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3D scheduling: high-level synthesis with floorplanning

Authors:

Jen-Pin Weng,

Alice C. ParkerAuthors Info & Claims

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

Pages 668 - 673

https://doi.org/10.1145/127601.127748

Published: 01 June 1991 Publication History

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Tatsuoka MWatanabe ROtsuka THasegawa TZhu QOkamura RLi XTakabatake T(2015)Physically aware high level synthesis design flowProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744893(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744893
HAMADA NSAITO H(2012)Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data ImplementationIEICE Transactions on Electronics10.1587/transele.E95.C.506E95-C:4(506-515)Online publication date: 2012
https://doi.org/10.1587/transele.E95.C.506
Cong JLiu BGroeneveld PSciuto DHassoun S(2012)A metric for layout-friendly microarchitecture optimization in high-level synthesisProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228587(1239-1244)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228587
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DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

June 1991

783 pages

ISBN:0897913957

DOI:10.1145/127601

Chairman:
A. Richard Newton
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1991

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DAC91: The 28th ACM/IEEE Design Automation Conference

June 17 - 22, 1991

California, San Francisco, USA

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Tatsuoka MWatanabe ROtsuka THasegawa TZhu QOkamura RLi XTakabatake T(2015)Physically aware high level synthesis design flowProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744893(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744893
HAMADA NSAITO H(2012)Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data ImplementationIEICE Transactions on Electronics10.1587/transele.E95.C.506E95-C:4(506-515)Online publication date: 2012
https://doi.org/10.1587/transele.E95.C.506
Cong JLiu BGroeneveld PSciuto DHassoun S(2012)A metric for layout-friendly microarchitecture optimization in high-level synthesisProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228587(1239-1244)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228587
Cong JLiu BLuo GPrabhakar RHu JKoh C(2012)Towards layout-friendly high-level synthesisProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160952(165-172)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2160916.2160952
Hamada NSaito HAtienza DXie YAyala JStevens K(2011)Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementationProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973042(157-162)Online publication date: 2-May-2011
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Kim TLiu XLin Y(2010)A global interconnect reduction technique during high level synthesisProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899883(695-700)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899883
OHCHI ATOGAWA NYANAGISAWA MOHTSUKI T(2009)Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register ArchitecturesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.3169E92-A:12(3169-3179)Online publication date: 2009
https://doi.org/10.1587/transfun.E92.A.3169
Krishnan VKatkoori S(2008)Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level SynthesisProceedings of the 21st International Conference on VLSI Design10.1109/VLSI.2008.85(641-646)Online publication date: 4-Jan-2008
https://dl.acm.org/doi/10.1109/VLSI.2008.85
Akira Ohchi Nozomu Togawa Masao Yanagisawa Tatsuo Ohtsuki (2008)High-level synthesis algorithms with floorplaning for distributed/shared-register architectures2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VDAT.2008.4542438(164-167)Online publication date: Apr-2008
https://doi.org/10.1109/VDAT.2008.4542438
Takayuki Obata Mineo Kaneko (2008)Concurrent skew and control step assignments in RT-level datapath synthesis2008 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2008.4541843(2018-2021)Online publication date: May-2008
https://doi.org/10.1109/ISCAS.2008.4541843
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Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems

Datapath synthesis using concurrent scheduling and allocation based on problem-space genetic algorithms

Early-release fair scheduling

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Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems

Datapath synthesis using concurrent scheduling and allocation based on problem-space genetic algorithms

Early-release fair scheduling

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