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Topology-based optimization of maximal sustainable throughput in a latency-insensitive system

Published: 04 June 2007 Publication History

Abstract

We consider the problem of optimizing the performance of a latency-insensitive system (LIS) where the addition of backpressure has caused throughput degradation. Previous works have addressed the problem of LIS performance in different ways. In particular, the insertion of relay stations and the sizing of the input queues in the shells are the two main optimization techniques that have been proposed. We provide a unifying framework for this problem by outlining which approaches work for different system topologies, and highlighting counterexamples where some solutions do not work. We also observe that in the most difficult class of topologies, instances with the greatest throughput degradation are typically very amenable to simplifications. The contributions of this paper include a characterization of topologies that maintain optimal throughput with fixed-size queues and a heuristic for sizing queues that produces solutions close to optimal in a fraction of the time.

References

[1]
S. M. Burns. Performance analysis and optimization of asynchronous circuits. PhD thesis, California Institute of Technology, Pasadena, CA, USA, 1991.
[2]
L. P. Carloni, K. L. McMillan, A. Saldanha, and A. L. Sangiovanni-Vincentelli. A methodology for "correct-by-construction" latency insensitive design. In Proc. Intl. Conf. on Computer-Aided Design, pages 309--315, San Jose, CA, Nov. 1999. IEEE.
[3]
L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli. Theory of latency-insensitive design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(9):1059--1076, Sept. 2001.
[4]
L. P. Carloni and A. L. Sangiovanni-Vincentelli. Performance analysis and optimization of latency insensitive systems. In Proc. of the Design Automation Conf., pages 361--367. ACM, 2000.
[5]
M. R. Casu and L. Macchiarulo. Issues in implementing latency insensitive protocols. In Proc. of the Conf. on Design, Automation and Test in Europe, pages 1390--1391, IEEE, 2004.
[6]
M. R. Casu and L. Macchiarulo. A new approach to latency insensitive design. In Proc. of the Design Automation Conf., pages 576--581. ACM, 2004.
[7]
M. R. Casu and L. Macchiarulo. Throughput-driven floorplanning with wire pipelining. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(5):663--675, May 2005.
[8]
R. L. Collins and L. P. Carloni. Topology-based optimization of maximal sustainable throughput in a latency-insensitive system. Technical Report CUCS-008-07, Columbia University, New York, New York, February 2007.
[9]
F. Commoner, A. W. Holt, S. Even, and A. Pnueli. Marked directed graphs. J. Comput. Syst. Sci., 5(5):511--523, 1971.
[10]
T. H. Cormen, C. Stein, R. L. Rivest, and C. E. Leiserson. Introduction to Algorithms. McGraw-Hill, 2001.
[11]
M. R. Garey and D. S. Johnson. Computers and Intractability. W. H. Freeman & Co., New York, 1979.
[12]
R. Lu and C. Koh. Performance optimization of latency insensitive systems through buffer queue sizing of communication channels. In Proc. Intl. Conf. on Computer-Aided Design, pages 227--231, Washington, DC, USA, 2003. IEEE Computer Society.
[13]
R. Lu and C. Koh. Performance analysis of latency insensitive systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 469--483, March 2006.
[14]
T. Murata. Circuit theoretic analysis and synthesis of marked graphs. IEEE Transactions on Circuit and Systems, 24(7), July 1977.
[15]
T. Murata. Petri nets: Properties, analysis and applications. Proceedings of the IEEE, 77(4):541--580, 1989.

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  • (2023)TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical DesignACM Transactions on Reconfigurable Technology and Systems10.1145/360933516:4(1-31)Online publication date: 5-Dec-2023
  • (2021)AutoBridgeThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439289(81-92)Online publication date: 17-Feb-2021
  • (2011)Throughput optimization for latency-insensitive system with minimal queue insertionProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950932(585-590)Online publication date: 25-Jan-2011
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      cover image ACM Conferences
      DAC '07: Proceedings of the 44th annual Design Automation Conference
      June 2007
      1016 pages
      ISBN:9781595936271
      DOI:10.1145/1278480
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      Published: 04 June 2007

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      1. latency-insensitive design
      2. performance analysis

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      View all
      • (2023)TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical DesignACM Transactions on Reconfigurable Technology and Systems10.1145/360933516:4(1-31)Online publication date: 5-Dec-2023
      • (2021)AutoBridgeThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439289(81-92)Online publication date: 17-Feb-2021
      • (2011)Throughput optimization for latency-insensitive system with minimal queue insertionProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950932(585-590)Online publication date: 25-Jan-2011
      • (2010)A new physical routing approach for robust bundled signaling on NoC linksProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785485(3-8)Online publication date: 16-May-2010
      • (2009)Leveraging local intracore information to increase global performance in block-based design of systems-on-chipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200915728:2(165-178)Online publication date: 1-Feb-2009
      • (2008)Performance optimization of elastic systems using buffer resizing and buffer insertionProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509559(442-448)Online publication date: 10-Nov-2008
      • (2008)Topology-Based Performance Analysis and Optimization of Latency-Insensitive SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200891427:12(2277-2290)Online publication date: 1-Dec-2008
      • (2008)Performance optimization of elastic systems using buffer resizing and buffer insertion2008 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2008.4681613(442-448)Online publication date: Nov-2008
      • (2007)Using functional independence conditions to optimize the performance of latency-insensitive systemsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326081(32-39)Online publication date: 5-Nov-2007

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