research-article

Performance optimization of elastic systems using buffer resizing and buffer insertion

Authors:

Dmitry Bufistov,

Jordi CortadellaAuthors Info & Claims

ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Pages 442 - 448

Published: 10 November 2008 Publication History

Abstract

Buffer resizing and buffer insertion are two transformation techniques for the performance optimization of elastic systems. Different approaches for each technique have already been proposed in the literature. Both techniques increase the storage capacity and can potentially contribute to improve the throughput of the system. Each technique offers a different trade-off between area cost and latency. This paper presents a method that combines both techniques to achieve the maximum possible throughput while minimizing the cost of the implementation. The provided method is based on mixed integer linear programming. A set of experiments is designed to show the feasibility of the approach.

References

[1]

J. Cong, "Challenges and opportunities for design innovations in nanometer technologies. in SRC working paper, Dec." 1997.

[2]

L. P. Carloni, K. L. McMillan, A. Saldanha, and A. L. Sangiovanni-Vincentelli, "A methodology for correct-by-construction latency-insensitive design," in Proc. Int. Conf. Computer-Aided Design (ICCAD), Nov. 1999, pp. 309--315.

Digital Library

[3]

L. P. Carloni and A. L. Sangiovanni-Vincentelli, "Coping with latency in SoC design," IEEE Micro, Special Issue on Systems on Chip, vol. 22, no. 5, p. 12, October 2002.

Digital Library

[4]

R. Lu and C.-K. Koh, "Performance optimization of latency insensitive systems through buffer queue sizing of communication channels," in Proc. Int. Conf. Computer-Aided Design (ICCAD), Nov. 2003, pp. 227--231.

Digital Library

[5]

J. Sparsø and S. Furber, Eds., Principles of Asynchronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, 2001.

Digital Library

[6]

J. Cortadella, M. Kishinevsky, and B. Grundmann, "Synthesis of synchronous elastic architectures," in Proc. ACM/IEEE Design Automation Conference, Jul. 2006, pp. 657--662.

Digital Library

[7]

P. A. Beerel, N.-H. Kim, A. Lines, and M. Davies, "Slack matching asynchronous designs," in Proc. of the 12th Int. Symp. on Asynchronous Circuits and Systems, 2006.

Digital Library

[8]

P. Prakash and A. J. Martin, "Slack matching quasi delay-insensitive circuits," in Proc. of the 12th Int. Symp. on Asynchronous Circuits and Systems, 2006.

Digital Library

[9]

F. Commoner, A. W. Holt, S. Even, and A. Pnueli, "Marked directed graphs," Journal of Computer and System Sciences, vol. 5, pp. 511--523, 1971.

Digital Library

[10]

T. Murata, "Petri Nets: Properties, analysis and applications," Proceedings of the IEEE, pp. 541--580, Apr. 1989.

[11]

R. Lu and C.-K. Koh, "Performance analysis of latency-insensitive systems." IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 25, no. 3, 2006.

Digital Library

[12]

R. Karp, "A characterization of the minimum cycle mean in a digraph," Discrete Mathematics, vol. 23, pp. 309--311, 1978.

[13]

A. Dasdan, S. Irani, and R. Gupta, "Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems," in Proc. 36th Design Automation Conference, 1999, pp. 37--42.

Digital Library

[14]

C. Ramchandani, "Analysis of asynchronous concurrent systems by timed Petri nets," Massachusetts Inst. of Tech., Tech. Rep. Project MAC Tech. Rep. 120, Feb. 1974.

Digital Library

[15]

S. M. Burns and A. J. Martin, "Performance analysis and optimization of asynchronous circuits," in Advanced Research in VLSI. MIT Press, 1991, pp. 71--86.

Digital Library

[16]

T. E. Williams, "Performance of iterative computation in self-timed rings," Journal of VLSI Signal Processing, vol. 7, no. 1/2, pp. 17--31, Feb. 1994.

Digital Library

[17]

C. V. Ramamoorthy and G. S. Ho, "Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets," IEEE Trans. on Software Engineering, vol. 6, no. 5, pp. 440--449, 1980.

Digital Library

[18]

K. Fazel, L. Li, M. Thornton, R. B. Reese, and C. Traver, "Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion," in GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI. New York, NY, USA: ACM, 2004, pp. 413--416.

Digital Library

[19]

R. Collins and L. Carloni, "Topology-based optimization of maximal sustainable throughput in a latency-insensitive system," in The Proceedings of the Design Automation Conference, June 2007, pp. 410--416.

Digital Library

[20]

S. M. Burns, "Performance analysis and optimization of asynchronous circuits," Ph.D. dissertation, California Institute of Technology, 1991.

Digital Library

[21]

J. Cochet-Terrasson, G. Cohen, S. Gaubert, M. M. Gettrick, and J.-P. Quadrat, "Numerical computation of spectral elements in max-plus algebra," Proc. of the IFAC Conference on System Structure and Control, july 1998.

[22]

"CPLEX," Available from http://www.ilog.com.

Cited By

Kishinevsky MGotmanov AViktorov Y(2011)Challenges in verifying communication fabricsProceedings of the Second international conference on Interactive theorem proving10.5555/2033939.2033944(18-21)Online publication date: 22-Aug-2011
https://dl.acm.org/doi/10.5555/2033939.2033944
Huang JChen YHo Y(2011)Throughput optimization for latency-insensitive system with minimal queue insertionProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950932(585-590)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950932
Galceran-Oms MGotmanov ACortadella JKishinevsky M(2011)Microarchitectural Transformations Using ElasticityACM Journal on Emerging Technologies in Computing Systems (JETC)10.1145/2043643.20436487:4(1-24)Online publication date: 1-Dec-2011
https://dl.acm.org/doi/10.1145/2043643.2043648
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Information

Published In

cover image ACM Conferences

ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

November 2008

855 pages

ISBN:9781424428205

General Chair:
Sani R. Nassif
IBM Austin Research Lab, Austin Texas
,
Program Chair:
Jaijeet Roychowdhury
Univ. of Minnesota, Minneapolis, MN

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)
IEEE CASS/CANDE

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IEEE Press

Publication History

Published: 10 November 2008

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ASE08

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SIGDA

ASE08: The International Conference on Computer-Aided Design

November 10 - 13, 2008

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Kishinevsky MGotmanov AViktorov Y(2011)Challenges in verifying communication fabricsProceedings of the Second international conference on Interactive theorem proving10.5555/2033939.2033944(18-21)Online publication date: 22-Aug-2011
https://dl.acm.org/doi/10.5555/2033939.2033944
Huang JChen YHo Y(2011)Throughput optimization for latency-insensitive system with minimal queue insertionProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950932(585-590)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950932
Galceran-Oms MGotmanov ACortadella JKishinevsky M(2011)Microarchitectural Transformations Using ElasticityACM Journal on Emerging Technologies in Computing Systems (JETC)10.1145/2043643.20436487:4(1-24)Online publication date: 1-Dec-2011
https://dl.acm.org/doi/10.1145/2043643.2043648
(2010)Elastic systemsProceedings of the Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2010.5558639(149-158)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/MEMCOD.2010.5558639
(2010)Minimizing back pressure for latency insensitive system synthesisProceedings of the Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2010.5558635(189-198)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/MEMCOD.2010.5558635

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