Soft-well digital circuit design
Abstract
References
Index Terms
- Soft-well digital circuit design
Recommendations
Hybrid TFET-MOSFET circuit
In this work, to increase the reliability of low power digital circuits in the presence of soft errors, the use of both III-V TFET- and III-V MOSFET-based gates is proposed. The hybridization exploits the facts that the transient currents generated by ...
Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation
The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this ...
Modeling pFET currents after soft breakdown at different gate locations
Special issue: Proceedings of the 13th biennial conference on insulating films on semiconductorspMOSFET currents after soft gate oxide breakdown are studied as a function of the breakdown position. The analysis draws on analogies with post-soft breakdown processes in a nMOSFET. The pMOSFET breakdown path is modeled as a narrow region of SiO2 with ...
Comments
Information & Contributors
Information
Published In
- General Chair:
- Antonio Petraglia,
- Program Chairs:
- Volnei A. Pedroni,
- Gert Cauwenberghs
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Check for updates
Author Tags
Qualifiers
- Article
Conference
Acceptance Rates
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 144Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in