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- ArticleSeptember 2007
Using majority logic to cope with long duration transient faults
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems designSeptember 2007, Pages 354–359https://doi.org/10.1145/1284480.1284572This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to long duration transient faults predicted for future technologies. The reasoning behind that prediction is explained, a new type of ...
- ArticleSeptember 2007
A software-based methodology for the generation of peripheral test sets based on high-level descriptions
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems designSeptember 2007, Pages 348–353https://doi.org/10.1145/1284480.1284571Nowadays, the use of Systems-on-Chip (SoCs) represents a very interesting solution, but also introduces some testing concerns. Up to now, researchers focused many efforts on the development of new software and hardware techniques for testing processors ...
- ArticleSeptember 2007
An optimized hybrid approach to provide fault detection and correction in SoCs
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems designSeptember 2007, Pages 342–347https://doi.org/10.1145/1284480.1284570An increasing number of safety-critical applications are based on Systems-on-Chip (SoCs), thus pushing a new wave of research aiming at the development of suitable techniques for ensuring their reliability. Several fault tolerance techniques have been ...
- ArticleSeptember 2007
Parallelized radix-4 scalable montgomery multipliers
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems designSeptember 2007, Pages 306–311https://doi.org/10.1145/1284480.1284562This paper describes a parallelized radix-4 scalable Montgomery multiplier implementation. The design does not require hardware multipliers, and uses parallelized multiplication to shorten the critical path. By left-shifting the sources rather than ...
- ArticleSeptember 2007
A soft error robust and power aware memory design
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems designSeptember 2007, Pages 300–305https://doi.org/10.1145/1284480.1284560A new RAM design, which is soft error robust and power aware, is proposed. The basic advantage of the proposed architecture is that it does achieve a considerable power saving potential, combined with potential for performance and reliability ...
- ArticleSeptember 2007
Total ionizing dose effects in switched-capacitor filters using oscillation-based test
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems designSeptember 2007, Pages 263–266https://doi.org/10.1145/1284480.1284551This paper studies long-term effects produced by ionizing radiation in a switched-capacitor filter, using the Oscillation Based Test (OBT) approach [1]. In this case, threshold voltage shifting is considered as one of the major concerning effects ...
- ArticleSeptember 2007
Soft-well digital circuit design
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems designSeptember 2007, Pages 196–201https://doi.org/10.1145/1284480.1284535In this paper we present a novel digital design technique called soft-well circuit design improving digital circuits in fine-pitch technology. Improved noise immunity, higher-speed and reduced static power leakage may be traded for somewhat increased ...
- ArticleSeptember 2007
A built-in current sensor for high speed soft errors detection robust to process and temperature variations
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems designSeptember 2007, Pages 190–195https://doi.org/10.1145/1284480.1284534Soft errors can be efficiently detected using built in current sensors connected to the transistors bulk, monitoring currents caused by ionizations in the substrate. However, electrical parameter variations can compromise the functional operation of the ...
- ArticleSeptember 2007
A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems designSeptember 2007, Pages 147–152https://doi.org/10.1145/1284480.1284525This paper presents an improved version of unified Montgomery multiplier architecture to reduce the critical path delay leading to higher data throughput. It is known that the critical path delay due to four-to-two carry save adders (CSAs), which have ...
