Article

A software-based methodology for the generation of peripheral test sets based on high-level descriptions

Authors:

Leticia M. V. Bolzani,

Edgar E. Sanchez,

Matteo Sonza ReordaAuthors Info & Claims

SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems design

Pages 348 - 353

https://doi.org/10.1145/1284480.1284571

Published: 03 September 2007 Publication History

Abstract

Nowadays, the use of Systems-on-Chip (SoCs) represents a very interesting solution, but also introduces some testing concerns. Up to now, researchers focused many efforts on the development of new software and hardware techniques for testing processors embedded in SoCs. However, the test of the surrounding peripherals has not been the subject of many research works, even if their importance within the entire system may be considerable.

In this paper we focus on Software-based Self-Test techniques for testing peripheral components within a SoC and explore the possibility that test generation only relies on high-level metrics. We outline a possible test generation and application flow, and discuss the suitability of different RT-level metrics. By exploiting a sample case study, we quantitatively evaluate the effectiveness of the different metrics and the practical viability of the considered approach. As a major contribution, the paper shows that for peripheral components the relationship between high-level and gate-level metrics is higher than for the general case.

References

[1]

D.K. Pradhan, Fault-Tolerant Computer System Design, Prentice Hall, 1996.

Digital Library

[2]

A. Cheng, A. Parashkevov, and C.C. Lim, "A Software Test Program Generator for Verifying System-on-Chip", HLDVT2005: IEEE International High Level Design Validation and Test Workshop 2005 2005, pp. 79--86

Digital Library

[3]

F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero, "An RT-level Fault Model with High Gate Level Correlation", HLDVT2000: IEEE International High Level Design Validation and Test Workshop, 2000

Digital Library

[4]

E. Sanchez, M. Sonza Reorda, G. Squillero, "Efficient Technique for Automatic Verification-Oriented Test Set Optimization", International Journal of Parallel Programming, Vol. 34, Num. 1, March 2006, pp. 93--109, Ed. Springer Netherlands.

Digital Library

[5]

S.Thatte, J.Abraham, "Test Generation for Microprocessors", IEEE Transactions on Computers, Vol. C-29, pp 429--441, 1980

Digital Library

[6]

F. Corno, P. Prinetto, M. Sonza Reorda, "Testability Analysis and ATPG on behaviour RT-level VHDL", ITC97, IEEE International Test Conference, 1997

Digital Library

[7]

S. Devadas, A. Ghosh, K. Keutzer, "An Observability-Based Code Coverage Metric for Functional Simulation", Proceedings IEEE/ACM International Conference on Computer Aided Design, 1996

Digital Library

[8]

F. Fallah, S. Devadas, K. Keutzer, "OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification", Proceedings 34th Design Automation Conference, 1998

Digital Library

[9]

http://www.opencores.org

[10]

U. Bieker, P. Marwedel, "Retargetable self-test program generation using constraint logic programming", 32nd ACM/IEEE Design Automation Conference, pp 605--611, 1995

Digital Library

[11]

C.A. Papachristou, F. Martin, M. Nourani, "Microprocessor Based Testing for Core-Based System on Chip", ACM/IEEE Design Automation Conference, pp 586--591, 1999

Digital Library

[12]

F. Corno, M. Sonza Reorda, G. Squillero, M. Violante, "On the Test of Microprocessor IP Cores", IEEE Design, Automation & Test in Europe, pp 209--213, 2001

Digital Library

[13]

Jimmy Liu Chien-Nan, Chang Chen-Yi, Jou Jing-Yang, Lai Ming-Chih, Juan Hsing-Ming, "A novel approach for functional coverage measurement in HDL Circuits and Systems", ISCAS2000: The 2000 IEEE International Symposium on Circuits and Systems, pp 217--220, 2000

[14]

E. Sanchez, M. Sonza Reorda and G. Squillero, "Test Program Generation From High-level Microprocessor Descriptions", Test and validation of hardware/software systems starting from system-level descriptions, Ed. M. Sonza Reorda, M. Violante, Z. Peng, Springer publisher, 179 p, ISBN: 1-85233-899-7, pp. 83--106, Dec. 2004

[15]

N. Kranitis, A. Paschalis, D. Gizopoulos, G. Xenoulis, "Software-based self-testing of embedded processors", IEEE Transactions on Computers, Vol 54, issue 4, pp 461--475, April 2005.

Digital Library

[16]

A. Manzone, P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda, "Integrating BIST techniques for on-line SoC testing," IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 235--240

Digital Library

[17]

P. Bernardi, L. Bolzani, A. Manzone, M. Osella, M. Violante, M. Sonza Reorda, "Software-based on-line test of communication peripherals in processor-based systems for automotive applications", MTV06: IEEE 7th International Workshop on Microprocessor Test and Verification, 2006.

Digital Library

[18]

K. Jayaraman, V. M. Vedula and J. A. Abraham, "Native Mode Functional Self-test Generation for System-on-Chip", IEEE International Symposium on Quality Electronic Design (ISQED'02), pp. 280--285, 2002.

Digital Library

[19]

L. Bolzani, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero, "An automated methodology for cogeneration of test blocks for peripheral cores", IOLTS 2007: IEEE International On-Line Testing Symposium, July 2007.

Digital Library

Cited By

Gurumurthy SBertanzetti DJakobsen PRearick J(2009)Cache-resident self-testing for I/O circuitry2009 International Test Conference10.1109/TEST.2009.5355549(1-8)Online publication date: Nov-2009
https://doi.org/10.1109/TEST.2009.5355549
Ravotto DSanchez ESchillaci MSquillero G(2008)An evolutionary methodology for test generation for peripheral cores via dynamic FSM extractionProceedings of the 2008 conference on Applications of evolutionary computing10.5555/1787943.1787968(214-223)Online publication date: 26-Mar-2008
https://dl.acm.org/doi/10.5555/1787943.1787968

Index Terms

A software-based methodology for the generation of peripheral test sets based on high-level descriptions
1. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Conferences

SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems design

September 2007

382 pages

ISBN:9781595938169

DOI:10.1145/1284480

General Chair:
Antonio Petraglia
UFRJ, Brazil
,
Program Chairs:
Volnei A. Pedroni
UTFPR, Brazil
,
Gert Cauwenberghs
UCSD

Copyright © 2007 ACM.

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Published: 03 September 2007

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SBCCI07

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SBCCI07: 20th Symposium on Integrated Circuits and System Design

September 3 - 6, 2007

Copacabana, Rio de Janeiro

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Gurumurthy SBertanzetti DJakobsen PRearick J(2009)Cache-resident self-testing for I/O circuitry2009 International Test Conference10.1109/TEST.2009.5355549(1-8)Online publication date: Nov-2009
https://doi.org/10.1109/TEST.2009.5355549
Ravotto DSanchez ESchillaci MSquillero G(2008)An evolutionary methodology for test generation for peripheral cores via dynamic FSM extractionProceedings of the 2008 conference on Applications of evolutionary computing10.5555/1787943.1787968(214-223)Online publication date: 26-Mar-2008
https://dl.acm.org/doi/10.5555/1787943.1787968

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