Article

A software-based methodology for the generation of peripheral test sets based on high-level descriptions

Authors:

Leticia M. V. Bolzani,

Edgar E. Sanchez,

Matteo Sonza ReordaAuthors Info & Claims

SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems design

Pages 348 - 353

https://doi.org/10.1145/1284480.1284571

Published: 03 September 2007 Publication History

Abstract

Nowadays, the use of Systems-on-Chip (SoCs) represents a very interesting solution, but also introduces some testing concerns. Up to now, researchers focused many efforts on the development of new software and hardware techniques for testing processors embedded in SoCs. However, the test of the surrounding peripherals has not been the subject of many research works, even if their importance within the entire system may be considerable.

In this paper we focus on Software-based Self-Test techniques for testing peripheral components within a SoC and explore the possibility that test generation only relies on high-level metrics. We outline a possible test generation and application flow, and discuss the suitability of different RT-level metrics. By exploiting a sample case study, we quantitatively evaluate the effectiveness of the different metrics and the practical viability of the considered approach. As a major contribution, the paper shows that for peripheral components the relationship between high-level and gate-level metrics is higher than for the general case.

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Digital Library

Cited By

Gurumurthy SBertanzetti DJakobsen PRearick J(2009)Cache-resident self-testing for I/O circuitry2009 International Test Conference10.1109/TEST.2009.5355549(1-8)Online publication date: Nov-2009
https://doi.org/10.1109/TEST.2009.5355549
Ravotto DSanchez ESchillaci MSquillero G(2008)An evolutionary methodology for test generation for peripheral cores via dynamic FSM extractionProceedings of the 2008 conference on Applications of evolutionary computing10.5555/1787943.1787968(214-223)Online publication date: 26-Mar-2008
https://dl.acm.org/doi/10.5555/1787943.1787968

Index Terms

A software-based methodology for the generation of peripheral test sets based on high-level descriptions
1. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Conferences

SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems design

September 2007

382 pages

ISBN:9781595938169

DOI:10.1145/1284480

General Chair:
Antonio Petraglia
UFRJ, Brazil
,
Program Chairs:
Volnei A. Pedroni
UTFPR, Brazil
,
Gert Cauwenberghs
UCSD

Copyright © 2007 ACM.

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Published: 03 September 2007

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SBCCI07

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SBCCI07: 20th Symposium on Integrated Circuits and System Design

September 3 - 6, 2007

Copacabana, Rio de Janeiro

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Gurumurthy SBertanzetti DJakobsen PRearick J(2009)Cache-resident self-testing for I/O circuitry2009 International Test Conference10.1109/TEST.2009.5355549(1-8)Online publication date: Nov-2009
https://doi.org/10.1109/TEST.2009.5355549
Ravotto DSanchez ESchillaci MSquillero G(2008)An evolutionary methodology for test generation for peripheral cores via dynamic FSM extractionProceedings of the 2008 conference on Applications of evolutionary computing10.5555/1787943.1787968(214-223)Online publication date: 26-Mar-2008
https://dl.acm.org/doi/10.5555/1787943.1787968

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