Article

Testability Analysis and ATPG on Behavioral RT-Level VHDL

Authors:

Fulvio Corno,

Paolo Prinetto,

Matteo Sonza ReordaAuthors Info & Claims

Proceedings of the IEEE International Test Conference

Pages 753 - 759

Published: 03 November 1997 Publication History

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Costa JMonteiro J(2013)Coverage-directed observability-based validation for embedded softwareACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244209018:2(1-20)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442090
Bolzani LSanchez EReorda MPetraglia APedroni VCauwenberghs G(2007)A software-based methodology for the generation of peripheral test sets based on high-level descriptionsProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284571(348-353)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.1145/1284480.1284571
Fummi FMarconcini CPravadelli G(2005)Logic-level mapping of high-level faultsIntegration, the VLSI Journal10.5555/1062115.171208338:3(467-490)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.5555/1062115.1712083
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e Abstract: In this paper, we present a method for analyzing the testability of a circuit during high level synthesis. The testability analysis returns values that represent the relative difficulty for computing test data, whatever the level of ...
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Published In

Proceedings of the IEEE International Test Conference

November 1997

1011 pages

ISBN:0780342097

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IEEE Computer Society

United States

Publication History

Published: 03 November 1997

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Costa JMonteiro J(2013)Coverage-directed observability-based validation for embedded softwareACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244209018:2(1-20)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442090
Bolzani LSanchez EReorda MPetraglia APedroni VCauwenberghs G(2007)A software-based methodology for the generation of peripheral test sets based on high-level descriptionsProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284571(348-353)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.1145/1284480.1284571
Fummi FMarconcini CPravadelli G(2005)Logic-level mapping of high-level faultsIntegration, the VLSI Journal10.5555/1062115.171208338:3(467-490)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.5555/1062115.1712083
Raik JNõmmeots TUbar R(2005)A New Testability Calculation Method to Guide RTL Test GenerationJournal of Electronic Testing: Theory and Applications10.1007/s10836-005-5288-521:1(71-82)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1007/s10836-005-5288-5
Rizk HPapachristou CWolff F(2004)Designing Self Test Programs for Embedded DSP CoresProceedings of the conference on Design, automation and test in Europe - Volume 210.5555/968879.969202Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968879.969202
Dimopoulos MLinardis P(2004)Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering TechniquesProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969069Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968878.969069
Ferrandi FFummi FSciuto D(2002)Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded ApplicationsIEEE Transactions on Computers10.1109/12.98000851:2(200-215)Online publication date: 1-Feb-2002
https://dl.acm.org/doi/10.1109/12.980008
Santos MGonçalves FTeixeira ITeixeira J(2002)RTL Design Validation, DFT and Test Pattern Generation for High Defects CoverageJournal of Electronic Testing: Theory and Applications10.1023/A:101499761071418:2(179-187)Online publication date: 1-Apr-2002
https://dl.acm.org/doi/10.1023/A%3A1014997610714
Fin AFummi FPravadelli G(2001)AMLETOProceedings of the 2001 IEEE International Test Conference10.5555/839296.843854Online publication date: 30-Oct-2001
https://dl.acm.org/doi/10.5555/839296.843854
Ferrandi FFerrara GSciuto DFin AFummi F(2001)Functional test generation for behaviorally sequential modelsProceedings of the conference on Design, automation and test in Europe10.5555/367072.367293(403-410)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367293
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Testability analysis and ATPG on behavioral RT-level VHDL

Analyzing Testability from Behavioral to RT Level

Validating behavioral vhdl descriptions

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