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Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels

Published: 30 September 2007 Publication History

Abstract

In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a region selection algorithm and a heuristic for run-time application mapping which minimizes the communication energy consumption, while still providing the required performance guarantees. The proposed technique allows for new applications to be easily added to the system platform with minimal inter-processor communication overhead. Moreover, our approach scales very well for large designs. Finally, the experimental results show as much as 50% communication energy savings compared to arbitrary mapping solutions.

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  • (2023)Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/359147019:3(1-26)Online publication date: 30-Jun-2023
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      cover image ACM Conferences
      CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
      September 2007
      284 pages
      ISBN:9781595938244
      DOI:10.1145/1289816
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 30 September 2007

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      Author Tags

      1. dynamic application mapping
      2. low-power
      3. networks-on-chip

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      ESWEEK07
      ESWEEK07: Third Embedded Systems Week
      September 30 - October 3, 2007
      Salzburg, Austria

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      Overall Acceptance Rate 280 of 864 submissions, 32%

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      Cited By

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      • (2024)High-performance application mapping in network-on-chip-based multicore systemsThe Journal of Supercomputing10.1007/s11227-024-06184-980:13(18573-18599)Online publication date: 18-May-2024
      • (2023)Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/359147019:3(1-26)Online publication date: 30-Jun-2023
      • (2023)A Case Study for Exploring the Impact of Optimized K - Means Algorithm on the Energy Efficiency of Multicore Systems2023 IEEE International Conference on High Performance Computing & Communications, Data Science & Systems, Smart City & Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys)10.1109/HPCC-DSS-SmartCity-DependSys60770.2023.00090(623-630)Online publication date: 17-Dec-2023
      • (2023)Heuristics-Enabled High-Performance Application Mapping in Network-on-Chip based Multicore Systems2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS)10.1109/COINS57856.2023.10189228(1-6)Online publication date: 23-Jul-2023
      • (2022)A Fast Heuristic for Improving the Energy Efficiency of Asymmetric VFI-Based Manycore SystemsIEEE Transactions on Sustainable Computing10.1109/TSUSC.2021.30927307:2(358-370)Online publication date: 1-Apr-2022
      • (2021)Energy-efficient task-resource co-allocation and heterogeneous multi-core NoC design in dark silicon eraMicroprocessors & Microsystems10.1016/j.micpro.2021.10405586:COnline publication date: 1-Oct-2021
      • (2018)Power- Thermal Aware Balanced Task-Resource Co-Allocation in Heterogeneous Many CPU-GPU Cores NoC in Dark Silicon Era2018 31st IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2018.8618557(260-265)Online publication date: Sep-2018
      • (2017)Efficient Mapping of Applications for Future Chip-Multiprocessors in Dark Silicon EraACM Transactions on Design Automation of Electronic Systems10.1145/305520222:4(1-26)Online publication date: 15-Jun-2017
      • (2017) A fault-aware low-power-dissipation dynamic mapping algorithm based on NoC 1 2017 20th International Conference on Electrical Machines and Systems (ICEMS)10.1109/ICEMS.2017.8056042(1-5)Online publication date: Aug-2017
      • (2017)Online multi-application mapping in photonic Network-on-Chip with mesh topologyOptical Switching and Networking10.1016/j.osn.2017.04.00225(100-108)Online publication date: Jul-2017
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