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- research-articleMarch 2024
Q-Memory Task Routing to Prevent Deadlocks in Ethernet Control with Memory Crossbar Switching
Optical Memory and Neural Networks (SPOMNN), Volume 33, Issue 1Pages 72–85https://doi.org/10.3103/S1060992X24010077AbstractIn Ethernet system, as a result of head of line blocking, numerous control data queues with high priority may cause priority queues to become overcrowded and their receiving DMAs (Direct Memory Access) to run out of buffer space, forcing them to ...
- research-articleSeptember 2023
STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators
ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 19, Issue 4Article No.: 32, Pages 1–20https://doi.org/10.1145/3531011Increasing deployment of Deep Neural Networks (DNNs) recently fueled interest in the development of specific accelerator architectures capable of meeting their stringent performance and energy consumption requirements. DNN accelerators can be organized ...
- research-articleJune 2023
Flumen: Dynamic Processing in the Photonic Interconnect
ISCA '23: Proceedings of the 50th Annual International Symposium on Computer ArchitectureArticle No.: 75, Pages 1–13https://doi.org/10.1145/3579371.3589110In chiplet-based heterogeneous architectures, electrical network-on-package (NoP) designs are typically over-provisioned with routers and channels to provide sufficient bandwidth during periods of high network load. Observing that there are ...
- research-articleOctober 2021
A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators
NOCS '21: Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-ChipPages 1–8https://doi.org/10.1145/3479876.3481602Increasing deployment of Deep Neural Networks (DNNs) in a myriad of applications, has recently fueled interest in the development of specific accelerator architectures capable of meeting their stringent performance and energy consumption requirements.
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- research-articleDecember 2020
A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs
ACM Transactions on Architecture and Code Optimization (TACO), Volume 18, Issue 1Article No.: 8, Pages 1–25https://doi.org/10.1145/3430699Exhaustive verification techniques do not scale with the complexity of today’s multi-tile Multi-processor Systems-on-chip (MPSoCs). Hence, runtime verification (RV) has emerged as a complementary method, which verifies the correct behavior of ...
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- research-articleDecember 2020
Automated synthesis of custom networks-on-chip for real world applications
ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided DesignArticle No.: 41, Pages 1–9https://doi.org/10.1145/3400302.3415656Network-on-Chip (NoC), using a packetized communication model presents a scalable interconnect infrastructure for System-on-Chip (SoC) architectures that meets its Performance, Power and Area (PPA) objectives. A typical NoC consists of building blocks ...
- research-articleSeptember 2020
Energy-Efficient On-Chip Networks through Profiled Hybrid Switching
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSIPages 241–246https://doi.org/10.1145/3386263.3406934Virtual channel (VC) flow control is the de facto choice for modern networks-on-chip (NoCs) to allow better utilization of the link bandwidth through buffering and packet switching (PS), which are also the sources of large power footprint and long per-...
- research-articleNovember 2019
Tightness and computation assessment of worst-case delay bounds in wormhole networks-on-chip
RTNS '19: Proceedings of the 27th International Conference on Real-Time Networks and SystemsPages 19–29https://doi.org/10.1145/3356401.3356408This paper addresses the problem of worst-case timing analysis in wormhole Networks-On-Chip (NoCs). We consider our previous work [5] for computing maximum delay bounds using Network Calculus, called the Buffer-Aware Worst-case Timing Analysis (BATA). ...
- research-articleNovember 2018
A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs
ACM Transactions on Embedded Computing Systems (TECS), Volume 17, Issue 5Article No.: 89, Pages 1–25https://doi.org/10.1145/3274665Executing multiple applications on a single MPSoC brings the major challenge of satisfying multiple quality requirements regarding real-time, energy, and so on. Hybrid application mapping denotes the combination of design-time analysis with run-time ...
- research-articleJanuary 2017
Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels
AISTECS '17: Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing SystemsPages 12–17https://doi.org/10.1145/3073763.3073765In some application domains (e.g., mission-critical systems), proactive detection of reliability threats or prompt fault containment are mandatory in order to avoid or limit the malfunctioning of electronic systems as an effect of the onset of permanent ...
- research-articleOctober 2016
Making the internet-of-things a reality: from smart models, sensing and actuation to energy-efficient architectures
CODES '16: Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System SynthesisArticle No.: 25, Pages 1–10https://doi.org/10.1145/2968456.2973272Advances in the physical sciences and engineering enable the development of internet-of-things (IoT) to understand, interface / interact and engineer physical world (systems). However, the deployment of multitude of wireless sensors and agents spanning ...
- posterSeptember 2016
POSTER: Fly-Over: A Light-Weight Distributed Power-Gating Mechanism For Energy-Efficient Networks-on-Chip
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and CompilationPages 413–414https://doi.org/10.1145/2967938.2974058Reducing static NoC power consumption is becoming critical for energy-efficient computing as technology scales down since NoCs are devouring a large fraction of the on-chip power budget. We propose Fly-Over (FLOV), a light-weight distributed mechanism ...
- research-articleAugust 2016
Cycle-Accurate Network on Chip Simulation with Noxim
ACM Transactions on Modeling and Computer Simulation (TOMACS), Volume 27, Issue 1Article No.: 4, Pages 1–25https://doi.org/10.1145/2953878The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance,...
- posterMarch 2016
NI + Router Microarchitecture for NoC-based Communication Systems
ANCS '16: Proceedings of the 2016 Symposium on Architectures for Networking and Communications SystemsPages 131–132https://doi.org/10.1145/2881025.2889484Modern communication systems are characterized by intensive computation signal processing algorithms. System-on-Chip implementations of these systems are generally based on Networks-on-Chip (NoC). The router and Network Interface (NI) are the main ...
- posterMarch 2016
Software Defined Networks-on-Chip for Multi/Many-Core Systems: A Performance Evaluation
ANCS '16: Proceedings of the 2016 Symposium on Architectures for Networking and Communications SystemsPages 129–130https://doi.org/10.1145/2881025.2889474By means of a management framework and programmable routing tables, Software Defined Network (SDN) architectures offer network's adaptability to today's computer systems. In Networks-on-Chip (NoC) based systems, management methods have been implemented ...
- research-articleSeptember 2015
Mathematical Modeling and Control of Multifractal Workloads for Data-Center-on-a-Chip Optimization
NOCS '15: Proceedings of the 9th International Symposium on Networks-on-ChipArticle No.: 21, Pages 1–8https://doi.org/10.1145/2786572.2786592Building autonomous data-centers-on-chip (DCoC) for exascale computing requires mathematical frameworks that account and exploit the non-stationary and multi-fractal characteristics of computation and communication workloads. Towards this end, relying on ...
- research-articleMarch 2015
A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platforms
DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & ExhibitionPages 253–258This paper describes a few fundamental challenges concerning the design of Network-on-Chip (NoC) based multicores as the backbone of cyber-physical systems (CPS) for personalized medicine. One fundamental challenge in designing such CPS architectures is ...
- ArticleMarch 2015
MACRON: The NoC-Based Many-Core Parallel Processing Platform and Its Applications in 4G Communication Systems
PDP '15: Proceedings of the 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based ProcessingPages 396–403https://doi.org/10.1109/PDP.2015.86The increasing demand of computation capacity has made many-core parallel processing (MPP) a compelling choice for computation-intensive applications. The networks-on-chip (NoC) architecture is an effective way to interconnect dozens of processing cores,...
- research-articleOctober 2014
HEFT: a hybrid system-level framework for enabling energy-efficient fault-tolerance in NoC based MPSoCs
CODES '14: Proceedings of the 2014 International Conference on Hardware/Software Codesign and System SynthesisArticle No.: 4, Pages 1–10https://doi.org/10.1145/2656075.2656087In emerging CMOS process technologies, network-on-chip (NoC) fabrics are increasingly becoming susceptible to transient faults. Fault-tolerance mechanisms that are typically employed in NoCs usually entail significant energy overheads that are expected ...
- research-articleOctober 2014
DAARM: design-time application analysis and run-time mapping for predictable execution in many-core systems
CODES '14: Proceedings of the 2014 International Conference on Hardware/Software Codesign and System SynthesisArticle No.: 34, Pages 1–10https://doi.org/10.1145/2656075.2656083Future many-core systems are envisaged to support the concurrent execution of varying mixes of different applications. Because of the vast number of binding options for such mixes on heterogeneous resources, enabling predictable application execution is ...