research-article

A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs

Authors:

Andreas Weichslgartner,

Stefan Wildermann,

Deepak Gangadharan,

Jürgen TeichAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 17, Issue 5

Article No.: 89, Pages 1 - 25

https://doi.org/10.1145/3274665

Published: 19 November 2018 Publication History

Abstract

Executing multiple applications on a single MPSoC brings the major challenge of satisfying multiple quality requirements regarding real-time, energy, and so on. Hybrid application mapping denotes the combination of design-time analysis with run-time application mapping. In this article, we present such a methodology, which comprises a design space exploration coupled with a formal performance analysis. This results in several resource reservation configurations, optimized for multiple objectives, with verified real-time guarantees for each individual application. The Pareto-optimal configurations are handed over to run-time management, which searches for a suitable mapping according to this information. To provide any real-time guarantees, the performance analysis needs to be composable and the influence of the applications on each other has to be bounded. We achieve this either by spatial or a novel temporal isolation for tasks and by exploiting composable networks-on-chip (NoCs). With the proposed temporal isolation, tasks of different applications can be mapped to the same resource, while, with spatial isolation, one computing resource can be exclusively used by only one application. The experiments reveal that the success rate in finding feasible application mappings can be increased by the proposed temporal isolation by up to 30% and energy consumption can be reduced compared to spatial isolation.

References

[1]

Benny Akesson, Anca Molnos, Andreas Hansson, Jude Ambrose Angelo, and Kees Goossens. 2011. Composability and predictability for independent application development, verification, and execution. In Multiprocessor System-on-Chip, Michael Hübner and Jrgen Becker (Eds.). Springer, New York, NY, 25--56.

[2]

Tobias Blickle, Jürgen Teich, and Lothar Thiele. 1998. System-level synthesis using evolutionary algorithms. Des. Autom. Embedded Syst. 3, 1 (Jan. 1998), 23--58.

Digital Library

[3]

Eduardo Wenzel Brião, Daniel Barcelos, and Flávio Rech Wagner. 2008. Dynamic task allocation strategies in MPSoC for soft real-time applications. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’08). ACM, New York, NY, 1386--1389.

Digital Library

[4]

Everton Carara, Gabriel Marchesan Almeida, Gilles Sassatelli, and Fernando Gehm Moraes. 2011. Achieving composability in NoC-based MPSoCs through QoS management at software level. In Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE). 407--412.

[5]

Ewerson Carvalho, Ney Calazans, and Fernando Moraes. 2007. Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs. In Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping. IEEE, Washington, DC, 34--40.

Digital Library

[6]

Weijia Che and Karam S. Chatha. 2010. Scheduling of synchronous data flow models on scratchpad memory based embedded processors. In 2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, November 7--11, 2010, Louis Scheffer, Joel R. Phillips, and Alan J. Hu (Eds.). IEEE, 205--212.

Digital Library

[7]

Junchul Choi, Hyunok Oh, Sungchan Kim, and Soonhoi Ha. 2012. Executing synchronous dataflow graphs on a SPM-based multicore architecture. In The 49th Annual Design Automation Conference 2012, DAC’12, San Francisco, CA, June 3--7, 2012, Patrick Groeneveld, Donatella Sciuto, and Soha Hassoun (Eds.). ACM, 664--671.

Digital Library

[8]

Chen-Ling Chou, Umit Y. Ogras, and Radu Marculescu. 2008. Energy- and performance-aware incremental mapping for networks on chip with multiple voltage levels. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 10 (2008), 1866--1879.

Digital Library

[9]

William J. Dally and Brian Towles. 2001. Route packets, not wires: On-chip inteconnection networks. In Proceedings of the 38th Annual Design Automation Conference (DAC’01). ACM, New York, NY, 684--689.

Digital Library

[10]

Robert Dick. 2010. Embedded System Synthesis Benchmarks Suite (E3S). http://ziyang.ewecs.umich.edu/dickrp/e3s/.

[11]

Christian Ferdinand. 2004. Worst case execution time prediction by static program analysis. In 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 26--30 April 2004, Santa Fe, New Mexico. 125--127.

[12]

Kees Goossens, John Dielissen, and Andrei Radulescu. 2005. Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design and Test of Computers 22, 5 (2005), 414--421.

Digital Library

[13]

Sebastian Graf, Felix Reimann, Michael Glaß, and Jürgen Teich. 2014. Towards scalable symbolic routing for multi-objective networked embedded system design and optimization. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014). ACM, New York, NY, Article 2, 10 pages.

Digital Library

[14]

Jan Heisswolf, Ralf König, Martin Kupper, and Jürgen Becker. 2013. Providing multiple hard latency and throughput guarantees for packet switching networks on chip. Comput. Electr. Eng. 39, 8 (Nov. 2013), 2603--2622.

Digital Library

[15]

Jörg Henkel, Lars Bauer, Nikil Dutt, Puneet Gupta, Sani Nassif, Muhammad Shafique, Mehdi Tahoori, and Norbert Wehn. 2013. Reliable on-chip systems in the nano-era: Lessons learnt and future trends. In Proceedings of the 50th Annual Design Automation Conference (DAC’13). ACM, New York, NY, Article 99, 10 pages.

Digital Library

[16]

Philip K. F. Hölzenspies, Johann L. Hurink, Jan Kuper, and Gerard J. M. Smit. 2008. Run-time spatial mapping of streaming applications to a heterogeneous multi-processor system-on-chip (MPSoC). In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’08). ACM, New York, NY, 212--217.

Digital Library

[17]

Jingcao Hu and Radu Marculescu. 2003. Energy-aware Mapping for tile-based NoC architectures under performance constraints. In Proceedings of the 2003 Asia and South Pacific Design Automation Conference (ASP-DAC’03). ACM, New York, NY, USA, 233--239.

Digital Library

[18]

Hanwoong Jung, Chanhee Lee, Shin-Haeng Kang, Sungchan Kim, Hyunok Oh, and Soonhoi Ha. 2014. Dynamic behavior specification and dynamic mapping for real-time embedded systems: HOPES approach. ACM Trans. Embedded Comput. Syst. 13, 4s (2014), 135:1--135:26.

Digital Library

[19]

Shin-Haeng Kang, Hoeseok Yang, Lars Schor, Iuliana Bacivarov, Soonhoi Ha, and Lothar Thiele. 2012. Multi-objective mapping optimization via problem decomposition for many-core systems. In IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, ESTIMedia 2012, Tampere, Finland, October 11--12, 2012. IEEE Computer Society, 28--37.

[20]

Sebastian Kobbe, Lars Bauer, Daniel Lohmann, Wolfgang Schröder-Preikschat, and Jörg Henkel. 2011. DistRM: Distributed resource management for on-chip many-core systems. In Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’11). ACM, New York, NY, 119--128.

Digital Library

[21]

Xianfeng Li, Yun Liang, Tulika Mitra, and Abhik Roychoudhury. 2007. Chronos: A timing analyzer for embedded software. Science of Computer Programming 69, 1 (2007), 56--67.

Digital Library

[22]

Martin Lukasiewycz, Michael Glaß, Christian Haubelt, and Jürgen Teich. 2008. Efficient symbolic multi-objective design space exploration. In Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21--24, 2008. IEEE, 691--696.

Digital Library

[23]

Giovanni Mariani, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Gianluca Palermo, Cristina Silvano, and Vittorio Zaccaria. 2010. An industrial design space exploration framework for supporting run-time resource management on multi-core systems. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8--12, 2010, Giovanni De Micheli, Bashir M. Al-Hashimi, Wolfgang Müller, and Enrico Macii (Eds.). IEEE Computer Society, 196--201.

Digital Library

[24]

Giovanni Mariani, Vlad Mihai Sima, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, and Koen Bertels. 2012. Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures. In 2012 Design, Automation 8 Test in Europe Conference 8 Exhibition, DATE 2012, Dresden, Germany, March 12--16, 2012, Wolfgang Rosenstiel and Lothar Thiele (Eds.). IEEE, 1379--1384.

Digital Library

[25]

Heikki Orsila, Tero Kangas, Erno Salminen, Timo D. Hämäläinen, and Marko Hännikäinen. 2007. Automated memory-aware application distribution for multi-processor system-on-chips. J. Syst. Archit. 53, 11 (Nov. 2007), 795--815.

Digital Library

[26]

Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, and Jürgen Teich. 2017. Predictable run-time mapping reconfiguration for real-time applications on many-core systems. In Proceedings of the 25th International Conference on Real-Time Networks and Systems (RTNS’17). ACM, New York, NY, 148--157.

Digital Library

[27]

Wei Quan and Andy D. Pimentel. 2015. A hybrid task mapping algorithm for heterogeneous MPSoCs. ACM Transactions on Embedded Computing Systems (TECS) 14, 1 (2015), 14:1--14:25.

Digital Library

[28]

Sascha Roloff, David Schafhauser, Frank Hannig, and Jürgen Teich. 2015. Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. In Proceedings of the 52nd Annual Design Automation Conference (DAC’15). ACM, New York, NY, Article 44, 6 pages.

Digital Library

[29]

Hamid Shojaei, Twan Basten, Marc Geilen, and Azadeh Davoodi. 2013. A fast and scalable multidimensional multiple-choice knapsack heuristic. TODAES 18, 4, Article 51 (2013), 32 pages.

Digital Library

[30]

H. Shojaei, A. Ghamarian, T. Basten, M. Geilen, S. Stuijk, and R. Hoes. 2009. A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management. In 2009 46th ACM/IEEE Design Automation Conference. 917--922.

Digital Library

[31]

Amit Kumar Singh, Akash Kumar, and Thambipillai Srikanthan. 2013. Accelerating throughput-aware run-time mapping for heterogeneous MPSoCs. ACM Trans. Des. Autom. Electron. Syst. 18, 1, Article 9 (Jan. 2013), 29 pages.

Digital Library

[32]

Amit Kumar Singh, Muhammad Shafique, Akash Kumar, and Jörg Henkel. 2013. Mapping on multi/many-core systems: Survey of current and emerging trends. In Proceedings of the 50th Annual Design Automation Conference (DAC’13). ACM, New York, NY, Article 1, 10 pages.

Digital Library

[33]

Peter van Stralen and Andy D. Pimentel. 2010. Scenario-based design space exploration of MPSoCs. In Proceedings of Conference on Computer Design (ICCD). 305--312.

[34]

Andreas Weichslgartner, Deepak Gangadharan, Stefan Wildermann, Michael Glaß, and Jürgen Teich. 2014. DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems. In Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES’14). ACM, New York, NY, Article 34, 10 pages.

Digital Library

[35]

Andreas Weichslgartner, Jan Heisswolf, Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jürgen Becker, and Jürgen Teich. 2015. Position paper: Towards hardware-assisted decentralized mapping of applications for heterogeneous noc architectures. In Proceedings of the 2nd International Workshop on Multi-Objective Many-Core Design (MOMAC) in Conjunction with International Conference on Architecture of Computing Systems (ARCS). IEEE, 1--4.

[36]

Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, and Jürgen Teich. 2018. Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Springer.

Digital Library

[37]

Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix C. Freiling, Michael Glaß, and Jürgen Teich. 2016. Design-time/run-time mapping of security-critical applications in heterogeneous MPSoCs. In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2016, Sankt Goar, Germany, May 23--25, 2016, Sander Stuijk (Ed.). ACM, 153--162.

Digital Library

[38]

Andreas Weichslgartner, Stefan Wildermann, and Jürgen Teich. 2011. Dynamic decentralized mapping of tree-structured applications on NoC architectures. In Proceedings of the 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS’11). ACM, New York, NY, 201--208.

Digital Library

[39]

Stefan Wildermann, Michael Glaß, and Jürgen Teich. 2014. Multi-objective distributed run-time resource management for many-cores. In Design, Automation 8 Test in Europe Conference 8 Exhibition, DATE 2014, Dresden, Germany, March 24--28, 2014. IEEE, 1--6.

Digital Library

[40]

Stefan Wildermann, Felix Reimann, Daniel Ziener, and Jürgen Teich. 2011. Symbolic design space exploration for multi-mode reconfigurable systems. In Proceedings of the 7th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’11). ACM, New York, NY, 129--138.

Digital Library

[41]

Stefan Wildermann, Andreas Weichslgartner, and Jürgen Teich. 2015. Design methodology and run-time management for predictable many-core systems. In Proceedings of the 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, ISORC Workshops 2015, Auckland, New Zealand, April 13--17, 2015. IEEE Computer Society, 103--110.

Digital Library

[42]

Reinhard Wilhelm, Jakob Engblom, Andreas Ermedahl, Niklas Holsti, Stephan Thesing, David Whalley, Guillem Bernat, Christian Ferdinand, Reinhold Heckmann, Tulika Mitra, Frank Mueller, Isabelle Puaut, Peter Puschner, Jan Staschulat, and Per Stenström. 2008. The worst-case execution-time problem—Overview of methods and survey of tools. ACM Transactions on Embedded Computing Systems (TECS) 7, 3, Article 36 (May 2008), 53 pages.

Digital Library

[43]

Pascal T. Wolkotte, Gerard J. M. Smit, Nikolay Kavaldjiev, Jens E. Becker, and Jürgen Becker. 2005. Energy model of networks-on-chip and a bus. In Proceedings of the 2005 International Symposium on System-on-Chip. 82--85.

[44]

Chantal Ykman-Couvreur, Prabhat Avasare, Giovanni Mariani, Gianluca Palermo, Cristina Silvano, and Vittorio Zaccaria. 2011. Linking run-time resource management of embedded multi-core platforms with automated design-time exploration. IET Computers 8 Digital Techniques 5, 2 (2011), 123--135.

[45]

Chantal Ykman-Couvreur, Vincent Nollet, Francky Catthoor, and Henk Corporaal. 2006. Fast multi-dimension multi-choice knapsack heuristic for MP-SoC run-time management. In International Symposium on System-on-Chip, 2006. 1--4.

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Spieck JWildermann STeich J(2022)A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCsACM Transactions on Design Automation of Electronic Systems10.1145/352923028:1(1-40)Online publication date: 31-Mar-2022
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Index Terms

A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 17, Issue 5

September 2018

183 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3278719

Editor:
Sandeep K. Shukla
Indian Institute of Technology, India

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Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 19 November 2018

Accepted: 01 August 2018

Revised: 01 April 2018

Received: 01 December 2015

Published in TECS Volume 17, Issue 5

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Transregional Collaborative Research Center “Invasive Computing”

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Cited By

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https://doi.org/10.1109/TNANO.2023.3237128
Weiss PSteinhorst S(2023)Predictable timing behavior of gracefully degrading automotive systemsDesign Automation for Embedded Systems10.1007/s10617-023-09271-x27:1-2(103-138)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1007/s10617-023-09271-x
Spieck JWildermann STeich J(2022)A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCsACM Transactions on Design Automation of Electronic Systems10.1145/352923028:1(1-40)Online publication date: 31-Mar-2022
https://dl.acm.org/doi/10.1145/3529230
Bose AGhosal P(2022)Scalable Run-time Task Mapping on BNoC Topology Focusing on Energy-efficiency2022 15th IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc)10.1109/NoCArc57472.2022.9911366(1-6)Online publication date: 2-Oct-2022
https://doi.org/10.1109/NoCArc57472.2022.9911366
Sahoo SRanjbar BKumar A(2021)Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective PaperJournal of Low Power Electronics and Applications10.3390/jlpea1101000711:1(7)Online publication date: 25-Jan-2021
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Weiss PElsabbahy SWcichslgartner ASteinhorst S(2021)Worst-Case Failover Timing Analysis of Distributed Fail-Operational Automotive Applications2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9473950(1294-1299)Online publication date: 1-Feb-2021
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Weiss PDaporta EWeichslgartner ASteinhorst S(2021)Checkpointing Period Optimization of Distributed Fail-Operational Automotive Applications2021 24th Euromicro Conference on Digital System Design (DSD)10.1109/DSD53832.2021.00066(389-395)Online publication date: Sep-2021
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Pourmohseni BGlaß MHenkel JKhdr HRapp MRichthammer VSchwarzer TSmirnov FSpieck JTeich JWeichslgartner AWildermann S(2020)Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future PerspectiveJournal of Low Power Electronics and Applications10.3390/jlpea1004003810:4(38)Online publication date: 17-Nov-2020
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Pourmohseni BSmirnov FKhdr HWildermann STeich JHenkel J(2019)Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems2019 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS46320.2019.00029(220-232)Online publication date: Dec-2019
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Gabriel DStechele WWildermann SEbeling WPöschel T(2019)Resource-Aware Parameter Tuning for Real-Time ApplicationsLectures on Quantum Statistics10.1007/978-3-030-18656-2_4(45-55)Online publication date: 25-Apr-2019
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