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A Desktop Computer with a Reconfigurable Pentium®

Published: 17 March 2008 Publication History
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  • Abstract

    Advancements in reconfigurable technologies, specifically FPGAs, have yielded faster, more power-efficient reconfigurable devices with enormous capacities. In our work, we provide testament to the impressive capacity of recent FPGAs by hosting a complete Pentium® in a single FPGA chip. In addition we demonstrate how FPGAs can be used for microprocessor design space exploration while overcoming the tension between simulation speed, model accuracy, and model completeness found in traditional software simulator environments. Specifically, we perform preliminary experimentation/prototyping with an original Socket 7 based desktop processor system with typical hardware peripherals running modern operating systems such as Fedora Core 4 and Windows XP; however we have inserted a Xilinx Virtex-4 in place of the processor that should sit in the motherboard and have used the Virtex-4 to host a complete version of the Pentium® microprocessor (which consumes less than half its resources). We can therefore apply architectural changes to the processor and evaluate their effects on the complete desktop system. We use this FPGA-based emulation system to conduct preliminary architectural experiments including growing the branch target buffer and the level 1 caches. In addition, we experimented with interfacing hardware accelerators such as DES and AES engines which resulted in a 27x speedup.

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    cover image ACM Transactions on Reconfigurable Technology and Systems
    ACM Transactions on Reconfigurable Technology and Systems  Volume 1, Issue 1
    Special edition on the 15th international symposium on FPGAs
    March 2008
    139 pages
    ISSN:1936-7406
    EISSN:1936-7414
    DOI:10.1145/1331897
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 17 March 2008
    Accepted: 01 December 2007
    Revised: 01 September 2007
    Received: 01 May 2007
    Published in TRETS Volume 1, Issue 1

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    Author Tags

    1. FPGA
    2. Pentium®
    3. accelerator
    4. architecture
    5. emulator
    6. exploration
    7. model
    8. operating system
    9. processor
    10. reconfigurable
    11. simulator

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    • (2018)Pipelined CPU Design With FPGA in Teaching Computer ArchitectureIEEE Transactions on Education10.1109/TE.2011.217522755:3(341-348)Online publication date: 29-Dec-2018
    • (2015)Area-Efficient Near-Associative Memories on FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/26294717:4(1-22)Online publication date: 23-Jan-2015
    • (2015)Reconfigurable Computing ArchitecturesProceedings of the IEEE10.1109/JPROC.2014.2386883103:3(332-354)Online publication date: Mar-2015
    • (2013)Area-efficient near-associative memories on FPGAsProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435298(191-200)Online publication date: 11-Feb-2013
    • (2012)A Survey of FPGA Dynamic Reconfiguration Design Methodology and ApplicationsInternational Journal of Embedded and Real-Time Communication Systems10.4018/jertcs.20120401023:2(23-39)Online publication date: Apr-2012
    • (2010)Carry-free vector-matrix multiplication on a dynamically reconfigurable optical platformApplied Optics10.1364/AO.49.00235249:12(2352)Online publication date: 14-Apr-2010

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