research-article

Federation: repurposing scalar cores for out-of-order instruction issue

Authors:

Kevin SkadronAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 772 - 775

https://doi.org/10.1145/1391469.1391666

Published: 08 June 2008 Publication History

Abstract

Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads that require better single-thread performance, a dedicated, larger core can help but comes at a large opportunity cost in the number of scalar cores that could be provisioned instead. This paper proposes a way to repurpose a pair of scalar cores into a 2-way out-of-order issue core with minimal area overhead. "Federating" scalar cores in this way nevertheless achieves comparable performance to a dedicated out-of-order core and dissipates less power as well.

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Cited By

Mummidi CKundu S(2023)A Neural Network-Based Approach to Dynamic Core Morphing for AMPs2023 IEEE International Symposium on Smart Electronic Systems (iSES)10.1109/iSES58672.2023.00013(4-9)Online publication date: 18-Dec-2023
https://doi.org/10.1109/iSES58672.2023.00013
Ta TAl-Hawaj KCebry NOu YHall EGolden CBatten C(2022)big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00025(181-198)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00025
Bedoukian PAdit NPeguero ESampson A(2021)Software-Defined Vector Processing on Manycore FabricsMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480099(392-406)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480099
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Index Terms

Federation: repurposing scalar cores for out-of-order instruction issue
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data

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cover image ACM Conferences

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

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Published: 08 June 2008

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DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Mummidi CKundu S(2023)A Neural Network-Based Approach to Dynamic Core Morphing for AMPs2023 IEEE International Symposium on Smart Electronic Systems (iSES)10.1109/iSES58672.2023.00013(4-9)Online publication date: 18-Dec-2023
https://doi.org/10.1109/iSES58672.2023.00013
Ta TAl-Hawaj KCebry NOu YHall EGolden CBatten C(2022)big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00025(181-198)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00025
Bedoukian PAdit NPeguero ESampson A(2021)Software-Defined Vector Processing on Manycore FabricsMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480099(392-406)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480099
Oliveira GGomez-Luna JOrosa LGhose SVijaykumar NFernandez ISadrosadati MMutlu O(2021)DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement BottlenecksIEEE Access10.1109/ACCESS.2021.31109939(134457-134502)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3110993
Venkataramani VPathania AShafique MMitra THenkel J(2018)Scalable Dynamic Task Scheduling on Adaptive Many-Core2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC2018.2018.00037(168-175)Online publication date: Sep-2018
https://doi.org/10.1109/MCSoC2018.2018.00037
Mittal S(2016)A Survey of Techniques for Architecting and Managing Asymmetric Multicore ProcessorsACM Computing Surveys10.1145/285612548:3(1-38)Online publication date: 8-Feb-2016
https://dl.acm.org/doi/10.1145/2856125
Chowdhury RKannepalli AKu SRotenberg E(2016)AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2016.7482096(214-224)Online publication date: Apr-2016
https://doi.org/10.1109/ISPASS.2016.7482096
Chen YCong JGill MReinman GXiao B(2015)Customizable ComputingSynthesis Lectures on Computer Architecture10.2200/S00650ED1V01Y201505CAC03310:3(1-118)Online publication date: 6-Jul-2015
https://doi.org/10.2200/S00650ED1V01Y201505CAC033
Mitra T(2015)Heterogeneous Multi-core ArchitecturesIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.8.518(51-62)Online publication date: 2015
https://doi.org/10.2197/ipsjtsldm.8.51
Zhang TJing NJiang KShu WWu MLiang X(2015)Buddy SMACM Transactions on Architecture and Code Optimization10.1145/274420212:2(1-23)Online publication date: 11-May-2015
https://dl.acm.org/doi/10.1145/2744202
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