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Memory latency effects in decoupled architectures with a single data memory module

Authors:

Lizyamma Kurian,

Paul T. Hulina,

Lee D. CoraorAuthors Info & Claims

ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture

Pages 236 - 245

https://doi.org/10.1145/139669.140380

Published: 01 April 1992 Publication History

Abstract

Decoupled computer architectures partition the memory access and execute functions in a computer program and achieve high performance by exploiting the fine-grain parallelism between the two. These architectures make use of an access processor to perform the data fetch ahead of demand by the execute process and hence are often less sensitive to memory access delays than conventional architectures. Past performance studies of decoupled computers used memory systems that are interleave or pipelined. We undertake a simulation study of the latency effects in decoupled computers when connected to a single, conventional non-interleaved data memory module so that the effect of decoupling is isolated from the improvement caused by interleaving. We compare decoupled computer performance to single processors with caches, study the memory latency sensitivity of the decoupled systems, and also perform simulations to determine the significance of data caches in a decoupled computer architecture. The Lawrence Livermore Loops and two signal processing algorithms are used as the simulation benchmark.

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Cited By

Wang ZNowatzki TManne SHunter HAltman E(2019)Stream-based memory access specialization for general purpose processorsProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322229(736-749)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322229
Ghose SHsieh KBoroumand AAusavarungnirun RMutlu O(2018)The Processing-in-Memory Paradigm: Mechanisms to Enable AdoptionBeyond-CMOS Technologies for Next Generation Computer Design10.1007/978-3-319-90385-9_5(133-194)Online publication date: 21-Aug-2018
https://doi.org/10.1007/978-3-319-90385-9_5
Crago NPatel S(2011)OUTRIDERACM SIGARCH Computer Architecture News10.1145/2024723.200007939:3(117-128)Online publication date: 4-Jun-2011
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Published In

cover image ACM Conferences

ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture

May 1992

439 pages

ISBN:0897915097

DOI:10.1145/139669

Chairman:
Allan Gottlieb
New York Unvi., New York, NY

ACM SIGARCH Computer Architecture News Volume 20, Issue 2
Special Issue: Proceedings of the 19th annual international symposium on Computer architecture (ISCA '92)
May 1992
429 pages
ISSN:0163-5964
DOI:10.1145/146628
Editor:
Allan Gotlieb
New York Univ., New York, NY
Issue’s Table of Contents

Copyright © 1992 Authors.

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SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1992

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ISCA92

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ISCA92: International Conference on Computer Architecture

May 19 - 21, 1992

Queensland, Australia

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Wang ZNowatzki TManne SHunter HAltman E(2019)Stream-based memory access specialization for general purpose processorsProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322229(736-749)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322229
Ghose SHsieh KBoroumand AAusavarungnirun RMutlu O(2018)The Processing-in-Memory Paradigm: Mechanisms to Enable AdoptionBeyond-CMOS Technologies for Next Generation Computer Design10.1007/978-3-319-90385-9_5(133-194)Online publication date: 21-Aug-2018
https://doi.org/10.1007/978-3-319-90385-9_5
Crago NPatel S(2011)OUTRIDERACM SIGARCH Computer Architecture News10.1145/2024723.200007939:3(117-128)Online publication date: 4-Jun-2011
https://dl.acm.org/doi/10.1145/2024723.2000079
Crago NPatel SIyer RYang QGonzález A(2011)OUTRIDERProceedings of the 38th annual international symposium on Computer architecture10.1145/2000064.2000079(117-128)Online publication date: 4-Jun-2011
https://dl.acm.org/doi/10.1145/2000064.2000079
Mameesh RFranklin MSalapura VGschwind MKnoop J(2010)Speculative-aware executionProceedings of the 19th international conference on Parallel architectures and compilation techniques10.1145/1854273.1854326(421-430)Online publication date: 11-Sep-2010
https://dl.acm.org/doi/10.1145/1854273.1854326
Mameesh RFranklin M(2005)SSTProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.98(662-665)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.98
Srinivasan SLebeck ABondi JSmith J(1998)Load latency tolerance in dynamically scheduled processorsProceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture10.5555/290940.290973(148-159)Online publication date: 1-Nov-1998
https://dl.acm.org/doi/10.5555/290940.290973
John LRadhakrisnan R(1996)Improving the parallelism and concurrency in decoupled architecturesProceedings of SPDP '96: 8th IEEE Symposium on Parallel and Distributed Processing10.1109/SPDP.1996.570325(130-137)Online publication date: 1996
https://doi.org/10.1109/SPDP.1996.570325
John LReddy VHulina PCoraor L(1995)Program balance and its impact on high performance RISC architecturesProceedings of the 1st IEEE Symposium on High-Performance Computer Architecture10.5555/527072.822633Online publication date: 22-Jan-1995
https://dl.acm.org/doi/10.5555/527072.822633
John LReddy VHulina PCoraor L(1995)Program balance and its impact on high performance RISC architecturesProceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture10.1109/HPCA.1995.386526(370-379)Online publication date: 1995
https://doi.org/10.1109/HPCA.1995.386526

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