research-article

Implementation of the PIPE Processor

Authors:

Matthew K. Farrens,

Andrew R. PleszkunAuthors Info & Claims

Computer, Volume 24, Issue 1

Pages 65 - 70

https://doi.org/10.1109/2.67195

Published: 01 January 1991 Publication History

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Abstract

The PIPE (parallel instruction with pipelined execution) processor, which is the result of a research project initiated to investigate high-performance computer architectures for VLSI implementation, is described. The lessons learned from the implementation are discussed. The most important result was the discovery that supporting architectural queues does not complicate the instruction issue logic and fees the processor clock rate from external memory speed influences. It was also found that the decision to support an instruction set with two instruction sizes and to allow consecutive two-parcel instruction issues profoundly affected the instruction fetch logic design. Other significant results concerned the issue logic, barrel shifter, cache control logic, and branch count.

References

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2. A.R. Pleszkun and E. Davidson, "A Structured Memory Access Architecture," Int'l Conf. Parallel Processing, Bellaire, Mich., Aug. 1983, pp. 461-471.

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4. M.K. Farrens, "The Design and Analysis of a High-Performance Single-Chip Processor," PhD thesis, Dept. of Electrical and Computer Eng., Univ. of Wisconsin at Madison, Wis., Aug. 1989.

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5. J.R. Goodman et al., "PIPE: A VLSI Decoupled Architecture," Proc. 12th Int'l Symp. Computer Architecture, June 1985, pp. 20- 27.

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6. M.K. Farrens and A.R. Pleszkun, "Improving the Performance of Small On-Chip Instruction Caches," Proc. 16th Int'l Symp. Computer Architecture, Vol. 17, No. 3, June 1989, pp. 234-241.

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7. J.L. Hennessy, "VLSI Processor Architecture," IEEE Trans. on Computers, Vol. C-33, No. 12, Dec. 1984, pp. 1221-1246.

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9. H.C. Young and J.R. Goodman, "A Simulation Study of Architectural Data Queues and Prepare-to-Branch Instruction," Proc. IEEE Int'l Conf. Computer Design: VLSI in Computers, Port Chester, NY, 1984, pp. 544-549.

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Cited By

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McFarlin DZilles C(2015)Branch vanguardACM SIGARCH Computer Architecture News10.1145/2872887.275040043:3S(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750400
McFarlin DZilles CMarr DAlbonesi D(2015)Branch vanguardProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750400(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750400
Sair SSherwood TCalder B(2003)A Decoupled Predictor-Directed Stream Prefetching ArchitectureIEEE Transactions on Computers10.1109/TC.2003.118394352:3(260-276)Online publication date: 1-Mar-2003
https://dl.acm.org/doi/10.1109/TC.2003.1183943
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Index Terms

Implementation of the PIPE Processor
1. Computer systems organization
  1. Architectures
    1. Serial architectures
      1. Pipeline computing
2. Hardware

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Reviews

Reviewer: David B. Skillicorn

The authors give an exceedingly brief overview of the PIPE processor, describe a single-chip nMOS implementation, and discuss some of the implications of the implementation experience for the design of the processor. The chief novelty of the processor design is the use of queues to handle the interface to memory. This allows split-phase memory access, visible to the programmer or compiler, so that the processor clock speed need not be coupled to the memory speed. The main fault of the paper is that the processor design is not described in sufficient detail to allow us to understand the conclusions drawn from the implementation experience. Also, the processor design seems, from the references, to be more than five years old, and the implementation uses very modest technology. Thus the applicability of the conclusions seems limited.

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Information

Published In

Computer Volume 24, Issue 1

Special issue on experimental research in computer architecture

January 1991

102 pages

ISSN:0018-9162

Editor:
Jon T. Butler
Naval Postgraduate School, Monterey, CA

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 January 1991

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McFarlin DZilles C(2015)Branch vanguardACM SIGARCH Computer Architecture News10.1145/2872887.275040043:3S(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750400
McFarlin DZilles CMarr DAlbonesi D(2015)Branch vanguardProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750400(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750400
Sair SSherwood TCalder B(2003)A Decoupled Predictor-Directed Stream Prefetching ArchitectureIEEE Transactions on Computers10.1109/TC.2003.118394352:3(260-276)Online publication date: 1-Mar-2003
https://dl.acm.org/doi/10.1109/TC.2003.1183943
Sherwood TSair SCalder BWolfe ASchlansker M(2000)Predictor-directed stream buffersProceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture10.1145/360128.360135(42-53)Online publication date: 1-Dec-2000
https://dl.acm.org/doi/10.1145/360128.360135
Jones GTopham NSmotherman MConte T(1997)A comparison of data prefetching on an access decoupled and superscalar machineProceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture10.5555/266800.266807(65-70)Online publication date: 1-Dec-1997
https://dl.acm.org/doi/10.5555/266800.266807
Kurian LHulina PCoraor L(1994)Memory Latency Effects in Decoupled ArchitecturesIEEE Transactions on Computers10.1109/12.32453943:10(1129-1139)Online publication date: 1-Oct-1994
https://dl.acm.org/doi/10.1109/12.324539
Kurian LHulina PCoraor L(1992)Memory latency effects in decoupled architectures with a single data memory moduleACM SIGARCH Computer Architecture News10.1145/146628.14038020:2(236-245)Online publication date: 1-Apr-1992
https://dl.acm.org/doi/10.1145/146628.140380
Kurian LHulina PCoraor LGottlieb A(1992)Memory latency effects in decoupled architectures with a single data memory moduleProceedings of the 19th annual international symposium on Computer architecture10.1145/139669.140380(236-245)Online publication date: 19-May-1992
https://dl.acm.org/doi/10.1145/139669.140380

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Cited By

Index Terms

Recommendations

Super-scalar processor design

Processor coupling: integrating compile time and runtime scheduling for parallelism

Super-Scalar Processor Design

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