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Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs

Published: 19 October 2008 Publication History

Abstract

Anton, a special-purpose parallel machine currently under construction, is the result of a significant hardware-software codesign effort that relied heavily on an architectural simulator. One of this simulator's many important roles is to support the development of embedded software (software that runs on Anton's ASICs), which is challenging for several reasons. First, the Anton ASIC is a heterogeneous multicore system-on-a-chip, with three types of embedded cores tightly coupled to special-purpose hardware units. Second, a standard 512-ASIC configuration contains a total of 6,656 distinct embedded cores, all of which must be explicitly modeled within the simulator. Third, a portion of the embedded software is dynamically generated at simulation time.
This paper discusses the various ways in which the Anton simulator addresses these challenges. We use a hardware abstraction layer that allows embedded software source code to be compiled without modification for either the simulation host or the hardware target. We report on the effectiveness of embedding golden-model testbenches within the simulator to verify embedded software as it runs. We also describe our hardware-software cosimulation strategy for dynamically generated embedded software. Finally, we use a methodology that we refer to as concurrent mixed-level simulation to model embedded cores within massively parallel systems. These techniques allow the Anton simulator to serve as an efficient platform for embedded software development.

References

[1]
M. Burtscher and I. Ganusov. Automatic synthesis of high-speed processor simulators. 37th International Symposium on Microarchitecture (MICRO-37), Portland, Oregon, Dec. 4-8, 2004, 55--66.
[2]
S. Dwarkadas, J. R. Jump and J. B. Sinclair. Execution-driven simulation of multiprocessors: address and timing analysis. ACM Trans. on Modeling and Computer Simulation, 4(4), Oct. 1994, 314--338.
[3]
L. Gao, S. Kraemer, R. Leupers, G. Ascheid and H. Meyr. A fast and generic hybrid simulation approach using C virtual machine. International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES '07), Salzburg, Austria, Oct. 2007, 3--12.
[4]
P. Gerin, S. Yoo, G. Nicolescu and A. A. Jerraya. Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures. 2001 Asia and South Pacific Design Automation Conference (ASP-DAC '01), Yokohama, Japan, Jan. 30-Feb. 2, 2001, 63--68.
[5]
D. Keppel. Tools and techniques for building fast portable threads packages. Technical Report UWCSE 93-05-06. University of Washington Dept. of Computer Science and Engineering, 1993.
[6]
S. Kraemer, L. Gao, J. Weinstock, R. Leupers, G. Ascheid and H. Meyr. HySim: a fast simulation framework for embedded software development. International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS '07), Salzburg, Austria, Sept. 30-Oct. 5, 2007, 75--80.
[7]
J. S. Kuskin, C. Young, J.P. Grossman, B. Batson, M. Deneroff, R. O. Dror and D. E. Shaw. Incorporating flexibility in Anton, a specialized machine for molecular dynamics simulation. 14th International Symposium on High-Performance Computer Architecture (HPCA-14), Salt Lake City, UT, Feb. 16-20, 2008, 343--354.
[8]
R. H. Larson, J. K. Salmon, R. O. Dror, M. Deneroff, R. C. Young, J.P. Grossman, Y. Shan, J. L. Klepeis and D. E. Shaw. High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation. 14th International Symposium on High-Performance Computer Architecture (HPCA-14), Salt Lake City, UT, Feb. 16-20, 2008, 331--342.
[9]
W. S. Mong and J. Zhu. DynamoSim: a trace-based dynamically compiled instruction set simulator. 2004 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '04), Washington, D.C., Nov. 7-11, 2004, 131--136.
[10]
A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H. Meyr and A. Hoffman. A Universal technique for fast and flexible instruction-set architecture simulation. 39th Conference on Design Automation (DAC '04), New Orleans, LA, June 10-14, 2002, 22--27.
[11]
M. Reshadi, P. Mishra and N. Dutt. Instruction set compiled simulation: a technique for fast and flexible set simulation. 40th Conference on Design Automation (DAC '03), Anaheim, CA, June 2-6, 2003, 758--763.
[12]
M. Rosenblum, S. A. Herrod, E. Witchel and A. Gupta. Complete computer system simulation: the SimOS approach. IEEE Parallel & Distributed Technology: Systems & Applications, 3(4), Winter 1995, 34--43.
[13]
D. E. Shaw, M. M. Deneroff, R. O. Dror, J. S. Kuskin, R. H. Larson, J. K. Salmon, C. Young, B. Batson, K. J. Bowers, J. C. Chao, M. P. Eastwood, J. Gagliardo, J.P. Grossman, C. R. Ho, D. J. Ierardi, I. Kolossváry, J. L. Klepeis, T. Layman, C. McLeavey, M. A. Moraes, R. Mueller, E. C. Priest, Y. Shan, J. Spengler, M. Theobald, B. Towles and S. C. Wang. Anton: a special-purpose machine for molecular dynamics simulation. 34th International Symposium on Computer Architecture (ISCA '07), San Diego, CA, June 9-13, 2007, 1--12.
[14]
P. K. Szwed, D. Marques, R. M. Buels, S. A. McKee and M. Schulz. SimSnap: fast-forwarding via native execution and application-level checkpointing. Eighth Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT '04), Madrid, Spain, Feb. 15, 2004, 65--74.
[15]
Tensilica, Inc. http://www.tensilica.com.
[16]
Tensilica, Inc. Xtensa XTMP. http://www.tensilica.com/products/sw_xtmp_xtsc.htm
[17]
J. E. Veenstra and R. Fowler. MINT: a front end for efficient simulations of shared-memory multiprocessors. Second International Workshop on Modeling, Analysis, and Simulation on Computer and Telecommunication Systems (MASCOTS '94), Durham, NC, Jan. 31-Feb. 2, 1994, 201--207.
[18]
E. Witchel and E. Rosenblum. Embra: fast and flexible machine simulation. ACM SIGMETRICS '96: Conference on Measurement and Modeling of Computer Systems, Philadelphia, PA, May 23-26, 1996, 68--79.
[19]
R. E. Wunderlich, T. F. Wenisch, B. Falsafi and J. C. Hoe. SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling. 30th International Symposium on Computer Architecture (ISCA '03), San Diego, CA, June 2003, 84--95.
[20]
J. Zhu and D. D. Gajski. A Retargetable, ultra-fast instruction set simulator. Design, Automation and Test in Europe Conference and Exhibition (DATE '99), Munich, Germany, March 9-12, 1999, 298--302.
[21]
V. Živojnović, S. Tjiang and J. Meyr. Compiled simulation of programmable DSP architectures. 1995 IEEE Workshop on VLSI Signal Processing, Sakai, Japan, 1995, 27--35.

Cited By

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  • (2013)The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputersProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488884(1-9)Online publication date: 29-May-2013
  • (2009)A design methodology for domain-optimized power-efficient supercomputingProceedings of the Conference on High Performance Computing Networking, Storage and Analysis10.1145/1654059.1654072(1-12)Online publication date: 14-Nov-2009

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cover image ACM Conferences
CODES+ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
October 2008
288 pages
ISBN:9781605584706
DOI:10.1145/1450135
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 19 October 2008

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Author Tags

  1. Anton
  2. embedded software
  3. simulation
  4. special-purpose hardware

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  • Research-article

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ESWEEK 08
ESWEEK 08: Fourth Embedded Systems Week
October 19 - 24, 2008
GA, Atlanta, USA

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CODES+ISSS '08 Paper Acceptance Rate 44 of 143 submissions, 31%;
Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

View all
  • (2013)The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputersProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488884(1-9)Online publication date: 29-May-2013
  • (2009)A design methodology for domain-optimized power-efficient supercomputingProceedings of the Conference on High Performance Computing Networking, Storage and Analysis10.1145/1654059.1654072(1-12)Online publication date: 14-Nov-2009

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