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FastHenry: a multipole-accelerated 3-D inductance extraction program

Authors:

M. Kamon,

M. J. Tsuk,

J. WhiteAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 678 - 683

https://doi.org/10.1145/157485.165090

Published: 01 July 1993 Publication History

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References

[1]

M. Kamon, M. Tsuk, C. Smithhisler, and J. White, "Efficient techniques for inductance extra~tion of complex 3-d geometries," in Proceedings o/the Int. Con}. on Comp. Aided Design, November 1992.

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P. A. Brennan, N. Raver, and A. Ruehli, "Three dimensional inductance computations with partial element equivalent circuits," IBM Journal of lies. and Develop., vol. 23, pp. 661-668, November 1979.

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K. N abors, S. Kim, and J. White, "Fast capacitance extraction of general three-dimensional structures," 1EEE Trans. on Microwave Theory and Techniques, vol. 40, pp. 1496-1506, July 1992.

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https://doi.org/10.1109/MCAS.2024.3376492
Stillig JParspour NEwert DJung T(2022)Feasibility Study on Machine Learning-based Method for Determining Self-and Mutual Inductance2022 International Seminar on Intelligent Technology and Its Applications (ISITIA)10.1109/ISITIA56226.2022.9855321(193-198)Online publication date: 20-Jul-2022
https://doi.org/10.1109/ISITIA56226.2022.9855321
Aretxabaleta IMartínez de Alegría IGarate JUgalde UMartín J(2022)Multiple current amplifier‐based gate driving for parallel operation of discrete SiC MOSFETsIET Power Electronics10.1049/pel2.1223215:4(317-324)Online publication date: 13-Jan-2022
https://doi.org/10.1049/pel2.12232
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Index Terms

FastHenry: a multipole-accelerated 3-D inductance extraction program
1. Hardware
2. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis
      1. Computations on matrices

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DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 July 1993

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June 14 - 18, 1993

Texas, Dallas, USA

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Analysis of power-performance for ultra-thin-body GeOI logic circuits

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Analysis of power-performance for ultra-thin-body GeOI logic circuits

Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs

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