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Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic

Authors:

Jean-Didier LegatAuthors Info & Claims

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

Pages 3 - 8

https://doi.org/10.1145/1594233.1594237

Published: 19 August 2009 Publication History

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Abstract

In this paper, we observe that minimum energy E_min of subthreshold logic dramatically increases when reaching 45nm node. We demonstrate by circuit simulation and analytical modeling that this increase comes from the combined effects of variability, gate leakage and DIBL. We then investigate the new impact of MOSFET parameters on E_min in nanometer technologies. We finally propose an optimum MOSFET selection intended for subthreshold circuit designers, which favors low-V_t mid-L_g devices in standard 45nm GP technology. The use of such optimum MOSFETs yields 35% E_min reduction for a benchmark multiplier with good speed performances and negligible area overhead.

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D. Bol, D. Flandre and J.-D. Legat, "Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits", ISLPED 2009.

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https://doi.org/10.1109/ETCM58927.2023.10309060
Oliveira DCardoso NBatista G(2022)Synthesis of Early Output Quasi Delay-Insensitive Combinational Circuits2022 IEEE ANDESCON10.1109/ANDESCON56260.2022.9989998(1-6)Online publication date: 16-Nov-2022
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Oliveira DVerducci OBatista G(2021)Synthesis of Quasi Delay Insensitive Asynchronous State Machines from Synchronous Specifications2021 IEEE XXVIII International Conference on Electronics, Electrical Engineering and Computing (INTERCON)10.1109/INTERCON52678.2021.9532653(1-4)Online publication date: 5-Aug-2021
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Index Terms

Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
1. Hardware
  1. Emerging technologies
  2. Hardware validation

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ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show that technology flavor and V_t selections shift minimum-energy point to ...

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Published In

cover image ACM Conferences

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

August 2009

452 pages

ISBN:9781605586847

DOI:10.1145/1594233

General Chairs:
Jörg Henkel
University of Karlsruhe
,
Ali Keshavarzi
Taiwan Semiconductor Manufacturing Company
,
Program Chairs:
Naehyuck Chang
Seoul National University
,
Tahir Ghani
Intel Corporation

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 19 August 2009

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ISLPED'09

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ISLPED'09: International Symposium on Low Power Electronics and Design

August 19 - 21, 2009

CA, San Fancisco, USA

Acceptance Rates

ISLPED '09 Paper Acceptance Rate 72 of 208 submissions, 35%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Oliveira DVerducci O(2023)Synthesis of QDI Combinational Circuits Based at the New Factorized DIMS2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM)10.1109/ETCM58927.2023.10309060(1-6)Online publication date: 10-Oct-2023
https://doi.org/10.1109/ETCM58927.2023.10309060
Oliveira DCardoso NBatista G(2022)Synthesis of Early Output Quasi Delay-Insensitive Combinational Circuits2022 IEEE ANDESCON10.1109/ANDESCON56260.2022.9989998(1-6)Online publication date: 16-Nov-2022
https://doi.org/10.1109/ANDESCON56260.2022.9989998
Oliveira DVerducci OBatista G(2021)Synthesis of Quasi Delay Insensitive Asynchronous State Machines from Synchronous Specifications2021 IEEE XXVIII International Conference on Electronics, Electrical Engineering and Computing (INTERCON)10.1109/INTERCON52678.2021.9532653(1-4)Online publication date: 5-Aug-2021
https://doi.org/10.1109/INTERCON52678.2021.9532653
Oliveira DCardoso NPinho MBatista G(2020)An Interface with Two-Phase Delay-Insensitive Global Communication for GALS Systems2020 IEEE ANDESCON10.1109/ANDESCON50619.2020.9272061(1-6)Online publication date: 13-Oct-2020
https://doi.org/10.1109/ANDESCON50619.2020.9272061
Levi IFish ALevi IFish A(2020)IntroductionDual Mode Logic10.1007/978-3-030-40786-5_1(1-24)Online publication date: 16-Dec-2020
https://doi.org/10.1007/978-3-030-40786-5_1
Sugii NKamohara SIkeda M(2020)The Future of Ultra-Low Power SOTB CMOS Technology and ApplicationsNANO-CHIPS 203010.1007/978-3-030-18338-7_6(47-88)Online publication date: 9-Jun-2020
https://doi.org/10.1007/978-3-030-18338-7_6
Verducci OOliveira DFaria L(2018)Synthesis of QDI AFSMs from XBM specifications2018 2nd Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)10.1109/PRIME-LA.2018.8370389(1-4)Online publication date: Mar-2018
https://doi.org/10.1109/PRIME-LA.2018.8370389
Saji JKamal S(2017)GDI logic implementation of uniform sized CSLA architectures in 45nm SOI technologyMicroprocessors & Microsystems10.1016/j.micpro.2017.01.00449:C(18-27)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.micpro.2017.01.004
Levi IFish A(2017)Alternative Logic Families for Energy-Efficient and High Performance Chip DesignGreen Photonics and Electronics10.1007/978-3-319-67002-7_6(139-172)Online publication date: 19-Nov-2017
https://doi.org/10.1007/978-3-319-67002-7_6
Nawaz KKamel DStandaert FFlandre D(2017)Scaling Trends for Dual-Rail Logic Styles Against Side-Channel Attacks: A Case-StudyConstructive Side-Channel Analysis and Secure Design10.1007/978-3-319-64647-3_2(19-33)Online publication date: 29-Jul-2017
https://doi.org/10.1007/978-3-319-64647-3_2
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