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Ultra-low power digital subthreshold logic circuits

Authors:

Hendrawan Soeleman,

Kaushik RoyAuthors Info & Claims

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

Pages 94 - 96

https://doi.org/10.1145/313817.313874

Published: 17 August 1999 Publication History

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Cited By

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Kumar ALorenzo R(2024)A low power static noise margin enhanced reliable 8 T SRAM cellMicrosystem Technologies10.1007/s00542-024-05662-730:6(729-738)Online publication date: 20-Apr-2024
https://doi.org/10.1007/s00542-024-05662-7
Panchal ASharma PGupta ANeema VTiwari NSindal R(2023)Improved reliability single loop single feed 7T SRAM cell for biomedical applicationsMemories - Materials, Devices, Circuits and Systems10.1016/j.memori.2023.1000574(100057)Online publication date: Jul-2023
https://doi.org/10.1016/j.memori.2023.100057
Kumar ALorenzo R(2023)Schmitter trigger-based single-ended stable 7T SRAM cellAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02185-5118:1(157-170)Online publication date: 23-Sep-2023
https://doi.org/10.1007/s10470-023-02185-5
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Index Terms

Ultra-low power digital subthreshold logic circuits
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Integrated circuits
    1. Logic circuits
    2. Semiconductor memory

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Published In

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

August 1999

295 pages

ISBN:158113133X

DOI:10.1145/313817

Chairmen:
Farid N. Najim
Univ. of Illinois at Urbana-Champaign
,
Jason Cong
UCLA
,
David Blaauw
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 August 1999

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ISLPED99

Sponsor:

SIGDA
IEEE-CAS

ISLPED99: International Symposium on Low Power Electronics and Design

August 16 - 17, 1999

California, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Kumar ALorenzo R(2024)A low power static noise margin enhanced reliable 8 T SRAM cellMicrosystem Technologies10.1007/s00542-024-05662-730:6(729-738)Online publication date: 20-Apr-2024
https://doi.org/10.1007/s00542-024-05662-7
Panchal ASharma PGupta ANeema VTiwari NSindal R(2023)Improved reliability single loop single feed 7T SRAM cell for biomedical applicationsMemories - Materials, Devices, Circuits and Systems10.1016/j.memori.2023.1000574(100057)Online publication date: Jul-2023
https://doi.org/10.1016/j.memori.2023.100057
Kumar ALorenzo R(2023)Schmitter trigger-based single-ended stable 7T SRAM cellAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02185-5118:1(157-170)Online publication date: 23-Sep-2023
https://doi.org/10.1007/s10470-023-02185-5
Tripathi B(2023)Subthreshold TransistorsAdvanced Ultra Low‐Power Semiconductor Devices10.1002/9781394167647.ch1(1-27)Online publication date: 27-Oct-2023
https://doi.org/10.1002/9781394167647.ch1
Kumari TTiwari PSingh JChang-Liao K(2022)Subthreshold Modeling of GAA MOSFET Including the Effect of Process-Induced Inclined SidewallsIEEE Transactions on Electron Devices10.1109/TED.2021.313382069:2(487-494)Online publication date: Feb-2022
https://doi.org/10.1109/TED.2021.3133820
Shiomi JTerada SIshihara TOnodera H(2022)Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits2022 IEEE 35th International System-on-Chip Conference (SOCC)10.1109/SOCC56010.2022.9908116(1-6)Online publication date: 5-Sep-2022
https://doi.org/10.1109/SOCC56010.2022.9908116
Kumar KDahiya MKumar MLakra P(2022)Optimization and Comparison of High Performance and Low Power NOR Gate Circuit Using Hybrid Model of Dynamic Voltage Scaling and MTCMOS TechniqueInnovations in Electrical and Electronic Engineering10.1007/978-981-19-1742-4_9(121-131)Online publication date: 27-Apr-2022
https://doi.org/10.1007/978-981-19-1742-4_9
Kakkar V(2019)An Ultra Low Power System Architecture for Implantable Medical DevicesIEEE Access10.1109/ACCESS.2018.27994227(111160-111167)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2018.2799422
Reyserhove HDehaene WReyserhove HDehaene W(2019)Near-Threshold Operation: Technology, Building Blocks and ArchitectureEfficient Design of Variation-Resilient Ultra-Low Energy Digital Processors10.1007/978-3-030-12485-4_2(17-51)Online publication date: 28-Mar-2019
https://doi.org/10.1007/978-3-030-12485-4_2
Zangi UFeldman NHadas TDayag NShor JFish A(2018)0.45 v and 18 μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)Journal of Low Power Electronics and Applications10.3390/jlpea80200148:2(14)Online publication date: 9-May-2018
https://doi.org/10.3390/jlpea8020014
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