A PD-based methodology to enhance efficiency in testbenches with random stimulation

Among the current verification techniques, functional verification has received important attention, since it represents an alternative that keeps HDL validation costs low throughout the circuit's design cycle. Functional verification is based in testbenches, and it works by exploring the whole (or relevant) model's functionality, applying sets of testcases. There are different techniques concerning testbenches operation, being the random stimulation an important approach, by which a huge number of testcases can be automatically created and applied. In testbench development, creation of random stimuli generators containing overlapping or invalid input parameter subspaces may occur, wasting computational time during testbench execution. In this work, we present a methodology to organize and apply random input stimuli by means of IP parameter domain, PD, formalism. The methodology provides the application of stimulus which: 1) belongs to the valid parameter subspace; 2) avoids repeated conditions; 3) covers the parameter subspaces uniformly. Moreover the methodology allows the automation of several tasks, making it efficient and less error-prone. Results on applying such a methodology are compared to cases where test vectors from the complete (unreduced, unorganized) verification space are generated manually, analyzing its relation to the coverage models specified for the design verification.