research-article

MPTLsim: a simulator for X86 multicore processors

Authors:

Dmitry PonomarevAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 226 - 231

https://doi.org/10.1145/1629911.1629974

Published: 26 July 2009 Publication History

Abstract

Current microprocessors are effectively a system-on-a-chip, as they incorporate processing cores, interconnections, shared and private caches and DRAM controllers on a single die. Consequently, it is imperative to have fast and accurate simulation tools for such systems; this paper such a tool for simulating all current and announced variants of multicore processors that use the predominant PC (X86, X86-64) instruction set, as well as external DRAM memory and buses. We discuss the major techniques used for speeding up the simulation and improving the overall accuracy, and the simulation of system-level details such as coherent caches, on-chip interconnections, memory bus and DRAM. We also demonstrate a 8-fold speedup against a widely-used popular tool.

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Shum CLau WMao TChung HTse NTsang KLai L(2018)DecompositionJ: Parallel and Deterministic Simulation of Concurrent Java Executions in Cyber-Physical SystemsIEEE Access10.1109/ACCESS.2018.28252546(21991-22010)Online publication date: 2018
https://doi.org/10.1109/ACCESS.2018.2825254
Zhang WWang HLu YChen HZhao W(2016)A Loosely-Coupled Full-System Multicore Simulation FrameworkIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.245549927:6(1566-1578)Online publication date: 1-Jun-2016
https://doi.org/10.1109/TPDS.2015.2455499
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Index Terms

MPTLsim: a simulator for X86 multicore processors
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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cover image ACM Conferences

DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 July 2009

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Intel Corporation

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DAC '09

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DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

California, San Francisco

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Cited By

Giorgi RKhalili FProcaccini M(2019)Translating Timing into an ArchitectureInternational Journal of Reconfigurable Computing10.1155/2019/26249382019Online publication date: 3-Nov-2019
https://dl.acm.org/doi/10.1155/2019/2624938
Shum CLau WMao TChung HTse NTsang KLai L(2018)DecompositionJ: Parallel and Deterministic Simulation of Concurrent Java Executions in Cyber-Physical SystemsIEEE Access10.1109/ACCESS.2018.28252546(21991-22010)Online publication date: 2018
https://doi.org/10.1109/ACCESS.2018.2825254
Zhang WWang HLu YChen HZhao W(2016)A Loosely-Coupled Full-System Multicore Simulation FrameworkIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.245549927:6(1566-1578)Online publication date: 1-Jun-2016
https://doi.org/10.1109/TPDS.2015.2455499
Clarke HTrouvé AMurakami K(2014)Accelerated design space pruning for CMP memory architecturesProceedings of the High Performance Computing Symposium10.5555/2663510.2663535(1-6)Online publication date: 13-Apr-2014
https://dl.acm.org/doi/10.5555/2663510.2663535
Bhardwaj NSenftleben MSchneider KTörngren M(2014)AbacusProceedings of the WESE'14: Workshop on Embedded and Cyber-Physical Systems Education10.1145/2829957.2829959(1-8)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2829957.2829959
Endo FCourousse DCharles H(2014)Micro-architectural simulation of in-order and out-of-order ARM microprocessors with gem52014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)10.1109/SAMOS.2014.6893220(266-273)Online publication date: Jul-2014
https://doi.org/10.1109/SAMOS.2014.6893220
Datta KMukherjee ACao GTenneti RVijendra Kumar Lakshmi VRavindran AJoshi B(2012)CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous ProcessorsJournal of Low Power Electronics and Applications10.3390/jlpea20100302:1(30-68)Online publication date: 1-Feb-2012
https://doi.org/10.3390/jlpea2010030
Fang ZMin QZhou KLu YHu YZhang WChen HLi JZang BGroeneveld PSciuto DHassoun S(2012)TransformerProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228381(106-114)Online publication date: 3-Jun-2012
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Patel AAfram FChen SGhose KStok LDutt NHassoun S(2011)MARSSProceedings of the 48th Design Automation Conference10.1145/2024724.2024954(1050-1055)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024954
Cook JCook JAlkohlani W(2011)A statistical performance model of the opteron processorACM SIGMETRICS Performance Evaluation Review10.1145/1964218.196423138:4(75-80)Online publication date: 29-Mar-2011
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