Cited By
View all- Marr BGeorge JDegnan BAnderson DHasler P(2010)Error immune logic for low-power probabilistic computingVLSI Design10.1155/2010/4603122010(1-9)Online publication date: 1-Jan-2010
A learning digital computer
Pages 617 - 618
Abstract
The concept of learning digital hardware is presented here. A proof of concept of a circuit that can arbitrarily control the current, and thus the switching speed and power consumption, of a digital circuit is given. This control of current is directly tuned by the feedback from the digital circuit itself, thus a learning digital computer. An argument for a completely new paradigm in digital computing follows whereby an entire system of learning digital circuits is proposed.
References
[1]
A. Basu, C. M. Twigg, S. Brink, P. Hasler, C. Petre, S. Ramakrishnan, S. Koziol, and C. Schlottmann. Rasp 2.8: A new generation of floating-gate based field programmable analog array. Proceedings, Custom Integrated Circuits Conference CICC, Sept. 2008.
[2]
A. Cassidy and A. Andreou. Dynamical digital silicon neurons. In IEEE Symposium on Biological Circuits and Systems (BioCAS), Nov. 2008.
[3]
P. Hasler and J. Dugar. Correlation learning rule in floating-gate pfet synapses. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Jan. 2001.
[4]
S.-C. Liu and R. Mockel. Temporarily learning floating gate vlsi synapses. In IEEE International Symposium on Circuits and Systems (ISCAS), May 2008.
Index Terms
- A learning digital computer
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Published In
July 2009
994 pages
ISBN:9781605584973
DOI:10.1145/1629911
Copyright © 2009 ACM.
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Sponsors
- EDAC: Electronic Design Automation Consortium
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE-CAS: Circuits & Systems
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 26 July 2009
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- Research-article
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DAC '09
Sponsor:
- EDAC
- SIGDA
- IEEE-CAS
DAC '09: The 46th Annual Design Automation Conference 2009
July 26 - 31, 2009
California, San Francisco
Acceptance Rates
Overall Acceptance Rate 1,770 of 5,499 submissions, 32%
Upcoming Conference
DAC '25
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Cited By
View all- Marr BGeorge JDegnan BAnderson DHasler P(2010)Error immune logic for low-power probabilistic computingVLSI Design10.1155/2010/4603122010(1-9)Online publication date: 1-Jan-2010
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