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Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors

Authors:

Thomas Baumann,

Doris Schmitt-Landsiedel,

Christian PachaAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 947 - 950

https://doi.org/10.1145/1629911.1630154

Published: 26 July 2009 Publication History

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Abstract

This work investigates the interrelation of performance and robustness against variability in industrial microprocessor designs. A novel analysis technique for variation-sensitive hardware and two figures of merit to quantify the robustness of a design against variations are proposed. Together with a multi-stage STA this enables an efficient application of low-V_T cell insertion and pulsed latch design to compensate for within-die delay variations. For the same speed margin of 5% on design level, a pulsed latch design of an ARM926 microprocessor shows a 2.5x higher robustness compared to a MS-FF design with selective low-V_T cell insertion.

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Cited By

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Minnella FCortadella JCasu MLazarescu MLavagno L(2023) Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops IEEE Access10.1109/ACCESS.2023.326580911(35830-35840)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3265809
Paik SHan IKim SShin Y(2019)Clock Gating Synthesis of Pulsed-Latch CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.218523531:7(1019-1030)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2012.2185235
Chuang YKim SShin YChang Y(2019)Pulsed-Latch Aware Placement for Timing-Integrity OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216571730:12(1856-1869)Online publication date: 3-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2011.2165717
Show More Cited By

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Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors
1. Hardware

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In this paper, a circuit design method for electrostatic discharge (ESD) protection is presented. It considers the gate floating state for ESD protection and negatively gate biased for leakage suppression under normal operations. The circuit is achieved ...

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DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 July 2009

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Bundesministerium für Bildung und Forschung

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DAC '09

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EDAC
SIGDA
IEEE-CAS

DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Minnella FCortadella JCasu MLazarescu MLavagno L(2023) Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops IEEE Access10.1109/ACCESS.2023.326580911(35830-35840)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3265809
Paik SHan IKim SShin Y(2019)Clock Gating Synthesis of Pulsed-Latch CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.218523531:7(1019-1030)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2012.2185235
Chuang YKim SShin YChang Y(2019)Pulsed-Latch Aware Placement for Timing-Integrity OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216571730:12(1856-1869)Online publication date: 3-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2011.2165717
Singh KJiao HHuisken JFatemi Hde Gyvez J(2018)Low power latch based design with smart retiming2018 19th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2018.8357308(329-334)Online publication date: Mar-2018
https://doi.org/10.1109/ISQED.2018.8357308
Elsharkasy WKhajeh AEltawil AKurdahi F(2017)Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed LatchesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2017.268043364:7(1803-1814)Online publication date: Jul-2017
https://doi.org/10.1109/TCSI.2017.2680433
Sangmin Kim Duckhwan Kim Youngsoo Shin (2013)Pulsed-latch ASIC synthesis in industrial design flow2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509621(356-361)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509621
Seungwhun Paik Seonggwan Lee Youngsoo Shin (2011)Retiming Pulsed-Latch Circuits With Regulating Pulse WidthIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.212693230:8(1114-1127)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.1109/TCAD.2011.2126932
Paik SShin Y(2010)Pulsed-latch circuits to push the envelope of ASIC design2010 International SoC Design Conference10.1109/SOCDC.2010.5682949(150-153)Online publication date: Nov-2010
https://doi.org/10.1109/SOCDC.2010.5682949

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Microarchitecture techniques to improve the design of superscalar microprocessors

Architectural and compiler techniques for energy reduction in high-performance microprocessors

A floating gate design for electrostatic discharge protection circuits

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