research-article

A parallel preconditioning strategy for efficient transistor-level circuit simulation

Authors:

Heidi K. Thornquist,

Eric R. Keiter,

Robert J. Hoekstra,

Erik G. BomanAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 410 - 417

https://doi.org/10.1145/1687399.1687477

Published: 02 November 2009 Publication History

Abstract

We describe a parallel computing approach for large-scale SPICE-accurate circuit simulation, which is based on a new strategy for the parallel preconditioned iterative solution of circuit matrices. This strategy consists of several steps, including singleton removal, block triangular form (BTF) reordering, hypergraph partitioning, and a block Jacobi pre-conditioner. Our parallel implementation makes use of a mixed load balance, employing a different parallel partition for the matrix load and solve. Based on message-passing, our circuit simulation code was originally designed for large parallel computers, but for the purposes of this paper we demonstrate that it also gives good parallel speedup in modern multi-core environments. We show that our new parallel solver outperforms a serial direct solver, a parallel direct solver and an alternative iterative solver on a set of circuit test problems.

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Index Terms

A parallel preconditioning strategy for efficient transistor-level circuit simulation

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cover image ACM Conferences

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
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Published: 02 November 2009

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November 2 - 5, 2009

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Cited By

Tench DWest EZhang VBender MChowdhury ADelayo DDellas JFarach-Colton MSeip TZhang K(2024)GraphZeppelin: How to Find Connected Components (Even When Graphs Are Dense, Dynamic, and Massive)ACM Transactions on Database Systems10.1145/364384649:3(1-31)Online publication date: 16-May-2024
https://dl.acm.org/doi/10.1145/3643846
Li LLiu ZLiu KShen SYu WTakahashi A(2023)Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit SimulationProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567882(339-345)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3567882
Tench DWest EZhang VBender MChowdhury ADellas JFarach-Colton MSeip TZhang KIves ZBonifati AEl Abbadi A(2022)GraphZeppelin: Storage-Friendly Sketching for Connected Components on Dynamic Graph StreamsProceedings of the 2022 International Conference on Management of Data10.1145/3514221.3526146(325-339)Online publication date: 10-Jun-2022
https://dl.acm.org/doi/10.1145/3514221.3526146
Cieślik S(2021)Mathematical Modeling of the Dynamics of Linear Electrical Systems with Parallel CalculationsEnergies10.3390/en1410293014:10(2930)Online publication date: 19-May-2021
https://doi.org/10.3390/en14102930
Azad ABuluc A(2019)LACC: A Linear-Algebraic Algorithm for Finding Connected Components in Distributed Memory2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS.2019.00012(2-12)Online publication date: May-2019
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Helal AJung CFeng WHanafy YZhao MChandra ARamakrishnan L(2018)CommAnalyzerProceedings of the 27th International Symposium on High-Performance Parallel and Distributed Computing10.1145/3208040.3208042(80-91)Online publication date: 11-Jun-2018
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Wang YZhang WLi PGong J(2017)Convergence-Boosted Graph Partitioning using Maximum Spanning Trees for Iterative Solution of Large Linear CircuitsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062215(1-6)Online publication date: 18-Jun-2017
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Chen XWang YYang HChen XWang YYang H(2017)Related WorkParallel Sparse Direct Solver for Integrated Circuit Simulation10.1007/978-3-319-53429-9_2(13-41)Online publication date: 12-Feb-2017
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