research-article

Low-power sub-threshold design of secure physical unclonable functions

Authors:

Dilip Kumar Krishnappa,

Prasad Shabadi,

Wayne BurlesonAuthors Info & Claims

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

Pages 43 - 48

https://doi.org/10.1145/1840845.1840855

Published: 18 August 2010 Publication History

Abstract

The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depends on minute uncontrollable process variations, a low supply voltage can benefit PUFs by providing high sensitivity to variations and low power consumption as well. Motivated by this, we explore the feasibility of sub-threshold arbiter PUFs in 45nm CMOS technology. By modeling process variations and interconnect imbalance effects at the post-layout design level, we optimize the PUF supply voltage for the minimum power-delay product and investigate the trade-offs on PUF uniqueness and reliability. Moreover, we demonstrate that such a design optimization does not compromise the security of PUFs regarding modeling attacks and side-channel analysis attacks. Our final 64-stage sub-threshold PUF design only needs 418 gates and consumes 0.047 pJ energy per cycle, which is very promising for low-power wireless sensing and security applications.

References

[1]

B. Gassend, D. Clarke, M. Van Dijk, and S. Devadas. Silicon physical random functions. In Proceedings of the 9th ACM conference on Computer and communications security, pages 148--160, 2002.

Digital Library

[2]

R. S. Pappu, B. Recht, J. Taylor, and N. Gershenfeld. Physical one-way functions. Science, 297(6):2026--2030, 2002.

[3]

G. E. Suh and S. Devadas. Physical unclonable functions for device authentication and secret key generation. In ACM/IEEE Design Automation Conference, pages 9--14, 2007.

Digital Library

[4]

J. Guajardo, S. S. Kumar, G. Schrijen, and P. Tuyls. FPGA intrinsic PUFs and their use for IP protection. In Proceedings of the Workshop on Cryptographic Hardware and Embedded Security, pages 63--80, September 2007.

Digital Library

[5]

D. E. Holcomb, W. P. Burleson, and K. Fu. Power-up SRAM State as an Identifying Fingerprint and Source of True Random Numbers. IEEE Transactions on Computers, 58(9):1198--1210, 2009.

Digital Library

[6]

D. Halperin, T. S. Heydt-Benjamin, B. Ransford, S. S. Clark, B. Defend, W. Morgan, K. Fu, T. Kohno, and W. H. Maisel. Pacemakers and implantable cardiac defibrillators: Software radio attacks and zero-power defenses. In Proceedings of Symposium on Security and Privacy, pages 129--142, 2008.

Digital Library

[7]

T. S. Heydt-Benjamin, D. V. Bailey, K. Fu, A. Juels, and T. OHare. Vulnerabilities in First-Generation RFID-enabled Credit Cards. In Financial Cryptography, 2007.

Digital Library

[8]

Y. Oren and A. Shamir. Remote password extraction from RFID tags. IEEE Transactions on Computers, 56(9):1292--1296, 2007.

Digital Library

[9]

K. Nohl and D. Evans. Reverse-engineering a cryptographic RFID tag. In USENIX Security Symposium, pages 185--193, 2008.

Digital Library

[10]

A. Juels and S. A. Weis. Authenticating pervasive devices with human protocols. Lecture notes in computer science, 3621: 293, 2005.

Digital Library

[11]

T. Eisenbarth, S. Kumar, C. Paar, A. Poschmann, and L. Uhsadel. A survey of lightweight-cryptography implementations. IEEE Design & Test of Computers, pages 522--533, 2007.

Digital Library

[12]

T. Popp, E. Oswald, and S. Mangard. Power analysis attacks and countermeasures. IEEE Design & Test of Computers, 24(6):535--543, 2007.

Digital Library

[13]

L. Lin and W. P. Burleson. Analysis and mitigation of process variation impacts on power-attack tolerance. In ACM/IEEE DAC, pages 238--243, 2009.

Digital Library

[14]

Verayo PUF RFID. http://www.verayo.com/product/pufr_d.html, 2008.

[15]

R. Maes, P. Tuyls, and I. Verbauwhede. Low-overhead implementation of a soft decision helper data algorithm for sram pufs. In CHES, pages 332--347. Springer-Verlag, 2009.

Digital Library

[16]

B. H. Calhoun, A. Wang, and A. P. Chandrakasan. Modeling and sizing for minimum energy operation in sub-threshold circuits. IEEE Journal of Solid-State Circuits, volume 40, pages 1778--1786, 2005.

[17]

S. Hanson, B. Zhai, D. Blaauw, D. Sylvester, A. Bryant, and X. Wang. Energy optimality and variability in subthreshold design. In ACM/IEEE ISLPED, pages 363--365, 2006.

Digital Library

[18]

V. Vivekraja and L. Nazhandali. Circuit-Level Techniques for Reliable Physically Uncloneable Functions. In IEEE HOST, pages 30--35, 2009.

Digital Library

[19]

International Technology Roadmap for Semiconductors. 2006 ITRS report, http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm

[20]

D. Bol, D. Kamel, D. Flandre, and J. D. Legat. Nanometer mosfet e_ects on the minimum-energy point of 45nm subthreshold logic. In ISLPED, pages 3--8, 2009.

Digital Library

[21]

S. Devadas, E. Suh, S. Paral, R. Sowell, T. Ziola, and V. Khandelwal. Design and implementation of puf-based "unclonable" RFID ICs for anti-counterfeiting and security applications. In IEEE International Conference on RFID, pages 58--64, 2008.

[22]

D. Lim. Extracting secret keys from integrated circuits. M.S. thesis Cambridge: Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol., May 2004.

[23]

M. Majzoobi, F. Koushanfar, and M. Potkonjak. Lightweight secure pufs. In ICCAD, pages 670--673, 2008.

Digital Library

[24]

B. E. Boser, I. M. Guyon, and V. N. Vapnik. A training algorithm for optimal margin classifiers. In Proceedings of the fifth annual workshop on Computational learning theory, pages 144--152, 1992.

Digital Library

[25]

T. Joachims. Making large scale SVM learning practical. http://svmlight.joachims.org/, 1999.

[26]

S. Mangard, E. Oswald, and T. Popp. Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer-Verlag New York, Inc., 2007.

Digital Library

[27]

D. Lim, J. W. Lee, B. Gassend, G. E. Suh, M. Van Dijk, and S. Devadas. Extracting secret keys from integrated circuits. IEEE Transactions on VLSI, 13(10):1200--1205, 2005.

Digital Library

Cited By

Khalil KIdriss HIdriss TBayoumi MKhalil KIdriss HIdriss TBayoumi M(2025)Improving the PUF’s ReliabilityLightweight Hardware Security and Physically Unclonable Functions10.1007/978-3-031-76328-1_8(59-86)Online publication date: 8-Jan-2025
https://doi.org/10.1007/978-3-031-76328-1_8
Dandin MMcFarlane NSajal MDehghandehnavi FNouri BDandin MMcFarlane NSajal MDehghandehnavi FNouri B(2024)Perimeter-Gated Single-Photon Avalanche Diode Arrays as Hardware Security PrimitivesSingle-Photon Avalanche Diodes and Photon Counting Systems10.1007/978-3-031-64334-7_5(91-116)Online publication date: 11-Jun-2024
https://doi.org/10.1007/978-3-031-64334-7_5
Lounis KDing SZulkernine M(2023)D2D-MAP: A Drone to Drone Authentication Protocol Using Physical Unclonable FunctionsIEEE Transactions on Vehicular Technology10.1109/TVT.2022.322461172:4(5079-5093)Online publication date: Apr-2023
https://doi.org/10.1109/TVT.2022.3224611
Show More Cited By

Index Terms

Low-power sub-threshold design of secure physical unclonable functions

Recommendations

Device Authentication by Physical Unclonable Functions
ICCUBEA '15: Proceedings of the 2015 International Conference on Computing Communication Control and Automation

Physical Unclonable Functions (PUFs) are very efficient circuits which are able to extract secrets from physical characteristic of any integrated circuit (IC). Wires and transistors have inherent delay characteristics. PUF designs make use of these ...
Threshold voltage degradation under high Vgs and low Vds on 200V SOI power devices

The hot-carrier degradation behavior of the 200V lateral insulated gate bipolar transistor and lateral diffused MOS transistor both on SOI substrates (SOI-LIGBT and SOI-LDMOS) under high Vgs and low Vds is experimentally investigated. It is shown that ...
Timing modeling for digital sub-threshold circuits
DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Despite an increasing interest in digital sub-threshold circuits little research has been dedicated to timing modeling in this voltage domain so far. Especially high timing variabilities makes proper modeling necessary to allow for the prediction of ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

August 2010

458 pages

ISBN:9781450301466

DOI:10.1145/1840845

General Chairs:
Vojin Oklobdzija
University of Texas, Dallas
,
Barry Pangle
Mentor Graphics
,
Naehyuck Chang
Seoul National University
,
Program Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign
,
Chris H. Kim
University of Minnesota

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

IEEE CAS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 August 2010

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ISLPED'10

Sponsor:

SIGDA

ISLPED'10: International Symposium on Low Power Electronics and Design

August 18 - 20, 2010

Texas, Austin, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

70
Total Citations
View Citations
508
Total Downloads

Downloads (Last 12 months)14
Downloads (Last 6 weeks)1

Reflects downloads up to 25 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Khalil KIdriss HIdriss TBayoumi MKhalil KIdriss HIdriss TBayoumi M(2025)Improving the PUF’s ReliabilityLightweight Hardware Security and Physically Unclonable Functions10.1007/978-3-031-76328-1_8(59-86)Online publication date: 8-Jan-2025
https://doi.org/10.1007/978-3-031-76328-1_8
Dandin MMcFarlane NSajal MDehghandehnavi FNouri BDandin MMcFarlane NSajal MDehghandehnavi FNouri B(2024)Perimeter-Gated Single-Photon Avalanche Diode Arrays as Hardware Security PrimitivesSingle-Photon Avalanche Diodes and Photon Counting Systems10.1007/978-3-031-64334-7_5(91-116)Online publication date: 11-Jun-2024
https://doi.org/10.1007/978-3-031-64334-7_5
Lounis KDing SZulkernine M(2023)D2D-MAP: A Drone to Drone Authentication Protocol Using Physical Unclonable FunctionsIEEE Transactions on Vehicular Technology10.1109/TVT.2022.322461172:4(5079-5093)Online publication date: Apr-2023
https://doi.org/10.1109/TVT.2022.3224611
Sajal MDandin M(2023)Challenge-Response Pair Space Enhancement for Imager-Based Physically Unclonable Functions2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS57524.2023.10405869(217-221)Online publication date: 6-Aug-2023
https://doi.org/10.1109/MWSCAS57524.2023.10405869
Sajal MDandin M(2023)Concealable Physically Unclonable Functions and Key Generation Using a Geiger Mode Imager2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10182123(1-5)Online publication date: 21-May-2023
https://doi.org/10.1109/ISCAS46773.2023.10182123
Anchana USingh SMogireddy MKadavergu E(2023)Design And Analysis Of Physical Unclonable Function2023 2nd International Conference for Innovation in Technology (INOCON)10.1109/INOCON57975.2023.10101289(1-4)Online publication date: 3-Mar-2023
https://doi.org/10.1109/INOCON57975.2023.10101289
Hemavathy SBhaaskaran V(2023)Arbiter PUF—A Review of Design, Composition, and Security AspectsIEEE Access10.1109/ACCESS.2023.326401611(33979-34004)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3264016
Podeti RPatri SPullakandam M(2023)Recursive Challenge Feed Arbiter Physical Unclonable Function (RC-FAPUF) In 180nm Process For Reliable Key Generation In IOT SecurityIETE Technical Review10.1080/02564602.2023.221453941:1(73-84)Online publication date: 18-May-2023
https://doi.org/10.1080/02564602.2023.2214539
Shariffuddin SSivamangai NNapolean ANaveenkumar RKamalnath SSaranya G(2022)Review on Arbiter Physical Unclonable Function and its Implementation in FPGA for IoT Security Applications2022 6th International Conference on Devices, Circuits and Systems (ICDCS)10.1109/ICDCS54290.2022.9780766(369-374)Online publication date: 21-Apr-2022
https://doi.org/10.1109/ICDCS54290.2022.9780766
Lokhande PNakhate S(2022)Comparative Analysis of Delay-Based and Memory-Based Physical Unclonable FunctionsIETE Technical Review10.1080/02564602.2022.214876240:5(641-652)Online publication date: 30-Nov-2022
https://doi.org/10.1080/02564602.2022.2148762
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten