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Trap-driven simulation with Tapeworm II

Published: 01 November 1994 Publication History

Abstract

Tapeworm II is a software-based simulation tool that evaluates the cache and TLB performance of multiple-task and operating system intensive workloads. Tapeworm resides in an OS kernel and causes a host machine's hardware to drive simulations with kernel traps instead of with address traces, as is conventionally done. This allows Tapeworm to quickly and accurately capture complete memory referencing behavior with a limited degradation in overall system performance. This paper compares trap-driven simulation, as implemented in Tapeworm, with the more common technique of trace-driven memory simulation with respect to speed, accuracy, portability and flexibility.

References

[1]
Agarwal, A., Hennessy, J. and Horowitz, M. Cache performance of operating system and multiprogramming workloads. ACM Transactions on Computer Systems 6 (Number 4): 393-431, 1988.
[2]
Agarwal, A., Sites, R. L. and Horowitz, M. ATUM: A new technique for capturing address traces using microcode, In Proceedings of the 13th International Symposium on Computer Architecture, Tokyo, Japan, IEEE, 119-127, 1986.
[3]
Alexander, C. A., Keshlear, W. M. and Briggs, F. Translation buffer performance in a UNIX environment. Computer Architecture News 13 (5): 2-14, 1985.
[4]
Anderson, T E., Levy, H. M., Bershad, B. N., et al. The interaction of architecture and operating system design, In Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, ACM, 108-119, 1991.
[5]
Appel, A. and Li, K. Virtual memory primitives for user programs, In The 4th International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, ACM, 96-107, 1991.
[6]
Borg, A., Kessler, R. E. and Wall, D. W. Generation and analysis of very long address traces, In The 17th Annual International Symposium on Computer Architecture, IEEE, 1990.
[7]
Chen, B. Software methods for system address tracing, In The 4th Workshop on Workstation Operating Systems, Napa, California, 1993.
[8]
Chert, B. and Bershad, B. The impact of operating system structure on memory system performance, In Proc. 14th Symposium on Operating System Principles, 1993.
[9]
Clark, D. Cache performance in the VAX-11/780. ACM Transactions on Computer Systems I: 24-37, 1983.
[10]
Cmelik, B. and Keppel, D. Shade: A Fast Instruction- Set Simulator for Execution Profiling, In SIGMETRiCS, Nashville, TN, ACM, 128-137, 1994.
[11]
Cvetanovic, Z. and Bhandarkar, D. Characterization of Alpha AXP performance using TP and SPEC Work- /oads, In The 21st Annual International Symposium on Computer Architecture, Chicago, Ill., IEEE, 1994.
[12]
Eggers, S. J., Keppel, D. R., Koldinger, E. J., et al. Techniques for efficient inline tracing on a shared-memory multiprocessor, In SIGMETRICS Conference on Measurement and Modeling of Computer Systems, ACM, 34-47, 1990.
[13]
Flanagan, K., Grimsrud, K., Archibald, J., et al. BACH: BYU address collection hardware. Brigham Young University. TR-A150-92.1. 1992.
[14]
Gee, J., Hill, M., Pnevmatikatos, D., et al. Cache Performance of the SPEC92 Benchmark Suite. IEEE Micro (August): 17-27, 1993.
[15]
Holliday, M. A. Techniques for cache and memory simulation using address reference traces. International journal in computer simulation 1: 129-15 I, 1991.
[16]
Hsu, P. Introduction to Shade. Sun Microsystems. 1989.
[17]
Kessler, R. Analysis of multi-megabyte secondary CPU cache memories. University of Wisconsin-Madison. 1991.
[18]
Kessler, R. and Hill, M. Page placement algorithms for large real-indexed caches. ACM Transaction on Computer Systems 10 (4): 338-359, 1992.
[19]
Larus, J. R. Abstract Execution: A technique for efficiently tracing programs. University of Wisconsin-Madison. 1990.
[20]
Larus, J. R. Efficient program tracing, iEEE Computer May, 1993: 52-60, 1993.
[21]
Lebeck, A. and Wood, D. Fast-Cache: A new abstraction for memory system simulation. The University of Wisconsin - Madison. Technical Report Number 1211. 1994.
[22]
Magnusson, P. S. A design for efficient simulation of a multtprocessor, In MASCOTS '93 - Proceedings of the 1993 Western Simulation Multiconference on International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, La Jolla, California, 1993.
[23]
Martonosi, M., Gupta, A. and Anderson, T. Mem- Spy: Analyzing memory system bottlenecks in programs, In SIGMETRICS Conference on the Measurement and Modeling of Computer Systems, ACM, 1992.
[24]
Martonosi, M., Gupta, A. and Anderson, T Effectiveness of trace sampling for performance debugging tools, In SIGMETRICS, Santa Clara, California, ACM, 248-259, 1993.
[25]
Mattson, R. L., Gecsei, J., Slutz, D. R., et al. Evaluation Techniques for Storage Hierarchies. IBM Systems Journal 9 (2): 78-117, 1970.
[26]
Report, M. Sebastopol, CA, MicroDesign Resources, 1992.
[27]
Report, M. Sebastopol, CA, MicroDesign Resources, 1993.
[28]
MIPS. RISCompiler Languages Prograrnrner~ Guide. MIPS, 1988.
[29]
Mogul, J. C. and Borg, A. The effect of context switches on cache performance, In Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clam, California, ACM, 75-84, 1991.
[30]
Nagle, D., Uhlig, R. and Mudge, T. Monster: A Tool for Analyzing the Interaction Between Operating Systems and Computer Architectures. The University of Michigan. CSE- TR- 147-92. 1992.
[31]
Nagle, D., Uhlig, R., Stanley, T, S. Sechrest, T Mudge, R. Brown, Design tradeoffs for software-managed TLBs, In The 20th Annual Intemational Symposium on Computer Architecture, San Diego, California, IEEE, 27-38, 1993.
[32]
Nagle, D., Uhlig, R., Mudge, T, et al. Optimal Allocation of On-chip Memory for Multiple-API Operating Systems, In The 21st International Symposium on Computer Architecture, Chicago, IL, 1994.
[33]
Ousterhout, J. Why aren't operating systems getting faster as fast as hardware. WRL Technical Note (TN-11): 1989.
[34]
Patel, K., Smith, B. C. and Rowe, L. A. Performance of a Software MPEG Video Decoder. University of California, Berkeley. 1992.
[35]
Puzak, T. Cache-memory design. University of Massachusetts. 1985.
[36]
Reinhardt, S., Hill, M., Larus, J., et al. The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers, In SIGMETRICS 93 (Special Issue of Performance Evaluation Review), Santa Clara, CA, ACM, 48-60, 1993.
[37]
Sites, R. L. and Agarwal, A. Multiprocessor cache analysis with ATUM, in The 15th Annual Intemational Symposium on Computer Architecture, Honolulu, Hawaii, IEEE, 186-195, 1988.
[38]
Smith, A. J. Cache Memories. Computing Surveys 14 (3): 473-530, 1982.
[39]
Smith, M. D. Tracing with pixie. Stanford University, Stanford, CA. 1991.
[40]
SPEC. The SPEC Benchmark Suite. SPEC Newsletter. 3: 3-4, 1991.
[41]
sugumar, R. Multi-configuration simulation algorithms for the evaluation of computer designs. University of Michigan. 1993.
[42]
Talluri, M. and Hill, M. Surpassing the TLB Performance of Superpages with Less Operating System Support, In ASPLOS-VI, San Jose, CA, ACM, In this proceedings, 1994.
[43]
Thompson, J. and Smith, A. Efficient (stack) algorithms for analysis of write-back and sector memories. ACM Transactions on Computer Systems 7 (1): 78-116, 1989.
[44]
Torrellas, J., Gupta, A. and Hennessy, J. Characterizing the caching and synchronization performance of multiprocessor operating system, In Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, ADM, 162-174, 1992.
[45]
Uhlig, R., Nagle, D., Mudge, T, Sechrest, S., Kernelbased Memory Simulation (Extended AbstracO, In SIGMET- RICS, Nashville, TN, University of Michigan, 286-287, 1994.
[46]
Uhlig, R., Nagle, D., Stanley, T., S. Sechrest, T Mudge, R. Brown, Design tradeoffs for software-managed TLBs. ACM Transactions on Computer Systems. To appear in Fall, 1994.

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cover image ACM Conferences
ASPLOS VI: Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
November 1994
341 pages
ISBN:0897916603
DOI:10.1145/195473
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 November 1994

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Author Tags

  1. TLB
  2. cache
  3. memory system
  4. trace-driven simulation
  5. trap-driven simulation

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  • (2005)Fast data-locality profiling of native executionProceedings of the 2005 ACM SIGMETRICS international conference on Measurement and modeling of computer systems10.1145/1064212.1064232(169-180)Online publication date: 6-Jun-2005
  • (2001)Trace-Driven Memory Simulation: A SurveyPerformance Evaluation: Origins and Directions10.1007/3-540-46506-5_5(97-139)Online publication date: 9-Nov-2001
  • (2000)Wisconsin Wind Tunnel IIIEEE Concurrency10.1109/4434.8951008:4(12-20)Online publication date: 1-Oct-2000
  • (1997)Generating Dynamic Program Analysis ToolsProceedings of the Australian Software Engineering Conference10.5555/786774.787198Online publication date: 28-Sep-1997
  • (1997)A technique for obtaining kernel mode address traces on a pentium-based Linux systemProceedings of the 35th annual ACM Southeast Conference10.1145/2817460.2817474(57-59)Online publication date: 2-Apr-1997
  • (1997)Trace-driven memory simulationACM Computing Surveys10.1145/254180.25418429:2(128-170)Online publication date: 1-Jun-1997
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