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Efficient (stack) algorithms for analysis of write-back and sector memories

Authors:

James G. Thompson and

Alan Jay SmithAuthors Info & Claims

ACM Transactions on Computer Systems (TOCS), Volume 7, Issue 1

Pages 78 - 117

https://doi.org/10.1145/58564.59296

Published: 01 January 1989 Publication History

Abstract

For the class of replacement algorithms known as stack algorithms, existing analysis techniques permit the computation of memory miss ratios for all memory sizes simultaneously in one pass over a memory reference string. We extend the class of computations possible by this methodology in two ways. First, we show how to compute the effects of copy-backs in write-back caches. The key observation here is that a given block is clean for all memory sizes less than or equal to C blocks and is dirty for all larger memory sizes. Our technique permits efficient computations for algorithms or systems using periodic write-back and/or block deletion. The second extension permits stack analysis simulation for sector (or subblock) caches in which a sector (associated with an address tag) consists of subsectors (or subblocks) that can be loaded independently. The key observation here is that a subsector is present only in caches of size C or greater. Load forward prefetching in a sector cache is shown to be a stack algorithm and is easily simulated using our technique. Running times for our methods are only slightly higher than for a simulation of a single memory size using nonstack techniques.

References

[1]

ARCHIBALD, J., AND BAER, J.-L. Cache coherence protocols: Evaluation using a multiprocessor simulation model. ACM Trans. Comput. Syst. 4, 4 (Nov. 1986), 273-298.

[2]

BAER, J.-L., AND SAGER, G. Dynamic improvement of locality in virtual memory systems. IEEE Trans. Softw. Eng. SE-2, 1 (Mar. 1976), 54-62.

[3]

BELADY, L.A. A study of replacement algorithms for virtual storage computers. IBM Syst. J. 5, 2 (1966), 78-101.

[4]

BELADY, L. A., NELSON, R. A., AND SHEDLER, G.S. An anomaly in space-time characteristics of certain programs running in a paging machine. Commun. ACM 12, 6 (June 1969), 349-353.

[5]

CHO, J., SACHS, H., AND SMITH, A.J. The memory architecture and the cache and memory management unit for the Fairchild CLIPPER processor. Univ. of California at Berkeley, Computer Science Div. Tech. Rep. UCB/CSD 86/289, Mar. 1986.

[6]

COFFMAN, S. G., AND RANDELL, B. Performance prediction for extended paged memories. Acta Inf. 1, I (1971), 1-13.

[7]

DENNING, P.J. On modeling program behavior. In Proceedings of the Spring Joint Computer Conference (AFIPS) 1972, pp. 937-944.

[8]

EASTON, M.C. Computation of cold-start miss ratios. IEEE Trans. Comput. TC-27, 5 (May 1978), 404-408.

[9]

GECSEI, J. Determining hit ratios in multilevel hierarchies. IBM J. Res. Dev. 18, 4 (July 1974), 316-327.

[10]

GOODMAN, J.R. Using cache memory to reduce processor-memory traffic. In Proceedings of the 1Oth International Symposium on Computer Architecture. (Stockholm, June, 1983). pp. 124-131.

[11]

GREENBERG, B. S. An experimental analysis of program reference patterns in the multics virtual memory. MAC Tech. Rep.-127, Cambridge, Mass., Jan. 1974.

[12]

GROSSMAN, C.P. Cache-DASD storage design for improving system performance. IBM Syst. J. 24, 3/4 (1985), 316-334.

[13]

HILL, M.D. Tech. Rep. UCB/CSD 87/381, Ph.D. dissertation, Univ. of California, Berkeley, Nov. 1987.

[14]

HILL, M. D., AND SMITH, A. J. Experimental evaluation of on-chip microprocessor cache memories. In Proceedings of the 11th Annual Symposium on Computer Architecture (Ann Arbor, Mich., June, 1984). pp. 158-166.

[15]

HORSPOOL, R. N., AND HUBERMAN, R. M. Demand prepaging algorithms with the memory inclusion property. In Proceedings of the 16th Annual Hawaii International Conference on System Sciences. 1983, pp. 138-145.

[16]

IEEE P896.1. Draft Standard, Backplane Bus (Futurebus). Nov. 1986.

[17]

KATZ, R., EGGERS, S., WOOD, D. A., PERKINS, C., AND SHELDON, R.G. Implementing a cache consistency protocol. In Proceedings of the 12th International Symposium on Computer Architecture (June 1985). pp. 276-283.

[18]

KENT, C. Cache Coherence in Distributed Systems. Ph.D. dissertation, Purdue Univ., West Lafayette, Ind., Aug. 1986.

[19]

KUBO, H., AND KOBAYASHI, M. A cost-oriented approach to optimal page size. In Proceedings of the 2nd USA-Japan Computer Conference (1975). pp. 258-263.

[20]

HOLLINGSWORTH, W., SACHS, H. AND SMITH, A.J. The CLIPPER processor: Instruction set architecture and implementation. Commun. ACM 32, 1 (Jan. 1989).

[21]

LmTAY, J.S. Structural aspects of the system/360 Model 85, part II: The cache. IBM Syst. J. 7, 1 (1968), 15-21.

[22]

MATTSON, R. L., GECSEI, J., SLUTZ, D., AND TRAIGER, I.L. Evaluation techniques for storage hierarchies. IBM Syst. J. 9, 2 (1970), 78-117.

[23]

OLKEN, F. Efficient methods for calculating the success function of fixed space replacement policies. Master's thesis, Univ. of California, Berkeley, Calif., May 1981.

[24]

OUSTERHOUT, J. K., DACOSTA, H., HARRISON, D., KUNZE, J. A., KUPFER, M., AND THOMPSON, J.G. A trace-driven analysis of the UNIX 4.2BSD File System. In Proceedings of the 10th Annual Symposium on Operating Systems Principles (Orcas Island, Wash., Dec. i-4, 1985). ACM, New York, 1985, pp. 15-24.

[25]

PATTERSON, D. A., GARRISON, P., HILL, M. D., Lmuels, D., NYBERG, C., SIPPEL, T. N., AND VAN DYKE, K.S. Architecture of a VLSI instruction cache for a RISC. In Proceedings of the 10th International Symposium on Computer Architecture (Stockholm, June 1983), pp. 108-116.

[26]

SHEDLER, G. S., AND SLUTZ, D.R. Derivation of miss ratios for merged access streams. IBM J. Res. Dev. 20, 5 (Sept. 1976), 505-517.

[27]

SILBERMAN, G.M. Stack processing techniques in delayed-staging storage hierarchies. Commun. ACM 26, II (Nov. 1983), 999-1007.

[28]

SLUTZ, D. R., AND TRAIGER, I.L. Determination of hit ratios for a class of staging hierarchies. IBM Res. Rep. RJ 1044, May 1972.

[29]

SMITH, A.J. Two methods for the efficient analysis of memory trace data. IEEE Trans. Softw. Eng. SE-3, 1 (Jan. 1977), 94-101.

[30]

SMITH, A. J. Sequential program prefetching in memory hierarchies. Computer 11, 2 (Dec. 1978), 7-21.

[31]

SMITH, A.J. Characterizing the storage process and its effect on the update of main memory by write-through. J. ACM 26, 1 (Jan. 1979), 6-27.

[32]

SMITH, A.J. Cache memories. ACM Comput. Surv. 14, 3 (Sept. 1982), 473-530.

[33]

SMITH, A.J. Cache evaluation and the impact of workload choice. In Proceedings o/the 12th Annual Symposium on Computer Architecture (Boston, Mass., June 1985). pp. 64-73.

[34]

SMITH, A.J. Disk cache--Miss ratio analysis and design considerations. A CM Trans. Comput. Syst., Aug. 1985, 161-203.

[35]

THOMPSON, J. Efficient analysis of caching systems. Ph.D. dissertation, Univ. of California, Berkeley; also Tech. Rep. UCB/CSD 87/374, Oct. 1987.

[36]

TOKUNAGA, T., HIRAI, Y., AND YAMAMOTO, S. Integrated disk cache systems with file adaptive control. In Proceedings of the IEEE Computer Society Conference (Washington, DC, Sept. 1980). IEEE, New York, 1980, pp. 412-416.

[37]

TRAIGER, I. L., AND SLUTZ, D.R. One pass techniques for the evaluation of memory hierarchies. IBM Res. Rep. RJ 892, Yorktown Heights, N.Y., July 1971.

[38]

Yu, F. S. Modeling the write behavior of computer programs. Ph.D. dissertation, Stanford Univ., Palo Alto, Calif., May 1976.

Cited By

Upadhyay BSudarshan T(2016)Design space exploration of cache memory — A survey2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)10.1109/ICEEOT.2016.7755102(2294-2297)Online publication date: Mar-2016
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Reviews

Reviewer: Dan Emanoil Grigoras

Thompson and Smith describe stack algorithms for the analysis of cache memories. They adopt the view that cache memories occupy one level in a hierarchy of memory types. The authors use trace-driven simulation to extend the stack analysis technique to the write-back and to sector or subblock caches, and they observe that “the ability to collect transfer ratios, considering both reads and writes, for all memory sizes in a single pass reduces simulation time by as much as 90% compared to running 8–10 individual simulations, making this metric much more reasonable to collect.” This well-illustrated paper excels by virtue of its clarity and completeness. The authors have taken a theoretical approach, and they address an audience of professionals. This subject is of major interest to computer systems designers, especially those working on multiprocessor caches and network file systems.

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cover image ACM Transactions on Computer Systems

ACM Transactions on Computer Systems Volume 7, Issue 1

Feb. 1989

116 pages

ISSN:0734-2071

EISSN:1557-7333

DOI:10.1145/58564

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Copyright © 1989 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 1989

Published in TOCS Volume 7, Issue 1

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https://doi.org/10.1109/ICEEOT.2016.7755102
Waldspurger CPark NGarthwaite AAhmad ISchindler JZadok E(2015)Efficient MRC construction with SHARDSProceedings of the 13th USENIX Conference on File and Storage Technologies10.5555/2750482.2750490(95-110)Online publication date: 16-Feb-2015
https://dl.acm.org/doi/10.5555/2750482.2750490
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https://dl.acm.org/doi/10.1145/2480741.2480749
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Alakarhu JNiittylahti J(2003)A method to estimate locality in the output of a cache level2003 46th Midwest Symposium on Circuits and Systems10.1109/MWSCAS.2003.1562566(1439-1442)Online publication date: 2003
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