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Random generation of test instances for logic optimizers

Authors:

Kazuo Iwama,

Kensuke HinoAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 430 - 434

https://doi.org/10.1145/196244.196452

Published: 06 June 1994 Publication History

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References

[1]

R. K. BRAYTON, R. RUDELL, A. L. SANGIOVANNI- VINCENTELLI, AND A. R. WANG, "Mis: A multiplelevel logic optimization system," IEEE Trans. CAD, 6, pp. 1062-1081, 1987.

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S. MUROGA, Y. KAMBAYASHI, H. C. LAI, AND J. N. CULLINEY, "The Transduction method- Design of logic networks based on permissible functions," IEEE Trans. Comput. 38, 10, 1989.

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E. M. SENTOVICH, K. J. SINGH, et al., "SIS: A system for sequential circuit synthesis," Memorandum No. UCB/ERL M92/41, 1992.

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Cited By

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Li BLin R(2022)Scalable Synthetic Circuit Generation using Geometry Embedding for CAD Tool Assessment2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937638(3239-3243)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937638
Vela ACruz-Duarte JOrtiz-Bayliss JAmaya I(2021)Tailoring Job Shop Scheduling Problem Instances Through Unified Particle Swarm OptimizationIEEE Access10.1109/ACCESS.2021.30764269(66891-66914)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3076426
Kundarewich PRose J(2006)Synthetic circuit generation using clustering and iterationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.82813223:6(869-887)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.828132
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Index Terms

Random generation of test instances for logic optimizers
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
  2. Hardware test
    1. Test-pattern generation and fault simulation

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Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 06 June 1994

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DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Li BLin R(2022)Scalable Synthetic Circuit Generation using Geometry Embedding for CAD Tool Assessment2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937638(3239-3243)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937638
Vela ACruz-Duarte JOrtiz-Bayliss JAmaya I(2021)Tailoring Job Shop Scheduling Problem Instances Through Unified Particle Swarm OptimizationIEEE Access10.1109/ACCESS.2021.30764269(66891-66914)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3076426
Kundarewich PRose J(2006)Synthetic circuit generation using clustering and iterationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.82813223:6(869-887)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.828132
Chang CCong JRomesis MXie M(2006)Optimality and scalability study of existing placement algorithmsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.82587023:4(537-549)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.825870
Hutton MRose JCorneil D(2006)Automatic generation of synthetic sequential benchmark circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2002.80045621:8(928-940)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2002.800456
Stroobandt DVerplaetse Pvan Campenhout J(2006)Generating synthetic benchmark circuits for evaluating CAD toolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.86364119:9(1011-1022)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.863641
Hutton MRose JGrossman JCorneil D(2006)Characterization and parameterized generation of synthetic combinational benchmark circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.72891917:10(985-996)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.728919
Velev M(2004)A new generation of ISCAS benchmarks from formal verification of high-level microprocessors2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)10.1109/ISCAS.2004.1329500(V-213-V-216)Online publication date: 2004
https://doi.org/10.1109/ISCAS.2004.1329500
Ratchev BHutton MBaeckler Gvan Antwerpen BTrimberger STessier R(2003)Verifying the correctness of FPGA logic synthesis algorithmsProceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays10.1145/611817.611837(127-135)Online publication date: 23-Feb-2003
https://dl.acm.org/doi/10.1145/611817.611837
Chang CCong JXie MYasuura H(2003)Optimality and scalability study of existing placement algorithmsProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119914(621-627)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119914
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Prioritizing random combinatorial test suites

Random test generation using concurrent logic simulation

Feedback-Directed Random Test Generation

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Prioritizing random combinatorial test suites

Random test generation using concurrent logic simulation

Feedback-Directed Random Test Generation

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