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The design of RPM: an FPGA-based multiprocessor emulator

Authors:

Michel DuboisAuthors Info & Claims

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Pages 60 - 66

https://doi.org/10.1145/201310.201321

Published: 15 February 1995 Publication History

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Abstract

Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) tools, mainly in synthesis tools, greatly simplify the design of large circuits. The RPM (Rapid Prototype Engine for Multiprocessors) Project leverages these two technological advances. Its goal is to develop a common hardware platform for the emulation of multiprocessor systems with different architectures.

For cost reasons, the use of FPGAs in RPM is limited to the memory controllers, while the rest of the emulator, including the processors, memories and interconnect, is built with off-the-shelf components. A flexible non-intrusive event logging mechanism is included at all levels of the memory hierarchy, making it possible to monitor the emulation in very fine detail. This paper presents the hardware design of RPM.

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Cited By

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Takamaeda-Yamazaki SSasakawa RSakaguchi YKise K(2011)An FPGA-based scalable simulation accelerator for tile architecturesACM SIGARCH Computer Architecture News10.1145/2082156.208216639:4(38-43)Online publication date: 19-Dec-2011
https://dl.acm.org/doi/10.1145/2082156.2082166
Chung EPapamichael MNurvitadhi EHoe JMai KFalsafi B(2009)ProtoFlexACM Transactions on Reconfigurable Technology and Systems10.1145/1534916.15349252:2(1-32)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1145/1534916.1534925
Bhattacharjee AContreras GMartonosi MNarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Full-system chip multiprocessor power evaluations using FPGA-based emulationProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1394010(335-340)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1394010
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Index Terms

The design of RPM: an FPGA-based multiprocessor emulator
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Integrated circuits
    1. Logic circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

February 1995

174 pages

ISBN:089791743X

DOI:10.1145/201310

Chairmen:
Pak K. Chan
Univ. of California at Santa Cruz, Santa Cruz
,
Jonathan Rose
Univ. of Toronto, Toronto, Ont., Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 1995

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FPGA95

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SIGDA

FPGA95: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 12 - 14, 1995

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all

Takamaeda-Yamazaki SSasakawa RSakaguchi YKise K(2011)An FPGA-based scalable simulation accelerator for tile architecturesACM SIGARCH Computer Architecture News10.1145/2082156.208216639:4(38-43)Online publication date: 19-Dec-2011
https://dl.acm.org/doi/10.1145/2082156.2082166
Chung EPapamichael MNurvitadhi EHoe JMai KFalsafi B(2009)ProtoFlexACM Transactions on Reconfigurable Technology and Systems10.1145/1534916.15349252:2(1-32)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1145/1534916.1534925
Bhattacharjee AContreras GMartonosi MNarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Full-system chip multiprocessor power evaluations using FPGA-based emulationProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1394010(335-340)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1394010
Chung ENurvitadhi EHoe JFalsafi BMai KHutton MChow P(2008)A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAsProceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays10.1145/1344671.1344684(77-86)Online publication date: 24-Feb-2008
https://dl.acm.org/doi/10.1145/1344671.1344684
Wee SCasper JNjoroge NTesylar YGe DKozyrakis COlukotun KDeHon AHutton M(2007)A practical FPGA-based framework for novel CMP researchProceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays10.1145/1216919.1216936(116-125)Online publication date: 18-Feb-2007
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Wawrzynek JPatterson DOskin MLu SKozyrakis CHoe JChiou DAsanovic K(2007)RAMPIEEE Micro10.1109/MM.2007.3927:2(46-57)Online publication date: 1-Mar-2007
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Grbic ASrbljic SVranesic Z(2001)Design of high-speed and flexible controllers in programmable logic devicesCanadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)10.1109/CCECE.2001.933624(1265-1271)Online publication date: 2001
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Miyazaki T(1998)Reconfigurable systems: a surveyProceedings of 1998 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1998.669520(447-452)Online publication date: 1998
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Dubois MJeong JSong YMoga A(1998)Rapid Hardware Prototyping on RPM-2IEEE Design & Test10.1109/54.70604215:3(112-118)Online publication date: 1-Jul-1998
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